After CoWoS, will the next generation of advanced packaging be CoPoS?
```
Driven by AI computing power demand, the system area of advanced packaging chips continues to expand. Traditional CoWoS technology (circular silicon interposer) has become a bottleneck for large-size AI chips due to limitations from photomask size and material characteristics.
In two research reports, Huatai Securities has clearly revealed an ongoing industry transformation: TSMC is using CoPoS technology (square glass substrate) to replace traditional CoWoS technology, breaking through the limits of advanced packaging’s lateral development.
The core reason for this transformation is: when chip area expands to more than 9.5 times the photomask size, traditional CoWoS faces physical bottlenecks such as warpage, high cost, and area limitations. CoPoS, on the other hand, offers larger sizes, lower signal loss, and a thermal expansion coefficient that matches silicon. According to TrendForce, TSMC will start building CoPoS pilot production lines in Q1 2026, with plans to complete them in June; Apple has also begun testing Samsung’s glass substrates for AI packaging. The industry chain’s migration to CoPoS has already substantively begun.
This means for investors that the incremental market driven by glass substrates, TGV (Through Glass Via), and RDL (Redistribution Layer) equipment is accelerating. Although TSMC’s mass production may not arrive until 2028, adoption in non-interposer fields like IC substrates and CPO may proceed faster than the market expects. The current pilot lines are already under construction, and relevant equipment and material suppliers are expected to be the first to benefit.
Core Driving Force: When Chips Get Too Big for ‘Circles’
The roadmap released by TSMC at its 2026 North America Technology Forum is the key to understanding all this. In 2024, its advanced packaging area is 3.3 reticles; in 2026, it rises to 5.5; in 2027, to 9.5. The latest target is: 14 reticles by 2028, and more than 40 by 2029. An area of 14 reticles is about 12,000 mm² – roughly two playing cards in size.
The demand for these “big chips” comes directly from AI giants like Nvidia, Google TPU, and Apple M-Ultra. However, TSMC’s current mainstream CoWoS-L solution (localized silicon bridge + organic RDL) faces severe warpage, process complexity, and physical limitations at such large sizes.
The solution is to ‘turn circles into squares’. CoPoS (Chip on Panel on Substrate) uses square glass panels instead of circular silicon interposers. The advantages of glass are: 1) The area can be made much larger, not limited by a round wafer; 2) Signal loss is extremely low, suited for high frequencies; 3) The thermal expansion coefficient can be tuned to match the chip, reducing warpage; 4) TGV through-vias can achieve a 50:1 aspect ratio, far exceeding the 10:1 of silicon through-vias (TSV), enabling higher interconnect density.
Incremental Opportunities: TGV and RDL Equipment as ‘Shovel Sellers’
CoPoS did not emerge from nothing; it is essentially the “panelization” evolution of CoWoS. This means the entire process chain needs to be rebuilt, and the greatest incremental opportunities are concentrated in the TGV and RDL segments.
TGV technology is like "wiring the nervous system" for the glass substrate. The process includes: laser-induced modification, etching, cleaning, double-sided electroplating, annealing, CMP (chemical mechanical polishing), etc. Among them, ultrafast laser drilling equipment is key. In addition, demand for panel-level horizontal electroplating and CMP equipment will increase significantly.
The RDL process is like "laying the blood vessels". As chip interconnect density rises, the number of RDL metal layers doubles and copper bump pitch shrinks to 5μm. This directly boosts demand for direct-write lithography, etching, thin film deposition, and inspection equipment. Especially AOI (Automated Optical Inspection) equipment, whose importance is unprecedented due to the new yield challenges of glass substrates.
Expectations & Timelines: Faster and Wider Than Imagined
The market’s mainstream opinion currently has two notable “expectation gaps”:
1. Application scope is wider than imagined. The market mainly focuses on CoPoS as an “interposer” to replace CoWoS. The research reports point out, however, that the low-loss and high-density advantages of glass substrates also give them ample room in IC substrate replacement, RF FOPLP packaging, and CPO (Co-Packaged Optics). Especially in optical modules of 1.6T and above, glass substrates, with excellent high-frequency performance and optical waveguide integration, are regarded as the core carrier for CPO.
2. Implementation may be faster than expected. Although TSMC has raised the CoWoS interposer cap to 14 reticles, which may delay the urgency for CoPoS mass adoption (TrendForce expects mass production in 2028), progress in new applications like IC substrates and CPO will speed up commercialization of glass substrates. For example, Intel already launched a sample EMIB package with 800µm glass substrate in early 2026.
CoPoS technology will reshape the advanced packaging value chain. Traditional packaging & testing plants need to extend upstream into glass substrates and material fields to master key capabilities like TGV and RDL; while panel manufacturers may expand downstream into packaging with their glass processing advantages, restructuring the industry division of labor.
From an investment logic perspective, three major links are expected to benefit: First, glass substrates and upstream materials—companies with full-process TGV capabilities and glass substrate mass production experience will benefit first; second, key equipment, including ultrafast laser drilling, panel-level plating, CMP flattening, direct-write lithography and inspection equipment, will see sharply increased demand; third, packaging and testing—packaging plants with experience in glass flip-chip processes are expected to expand into TGV advanced packaging. As TSMC’s pilot lines advance and downstream customer verification takes off, incremental opportunities in these segments will gradually open.
Risk Warning and DisclaimerThe market has risks, investment should be cautious. This article does not constitute personal investment advice and does not take into account individual users' specific investment objectives, financial situations, or needs. Users should consider whether any opinions, views, or conclusions in this article fit their particular situation. You are responsible for your own investment decisions. ```