After two years, SK Hynix and TSMC leaders meet again to discuss cooperation in HBM and advanced packaging fields.

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As the deep integration of the AI chip supply chain accelerates, the cooperation between the two giants in memory and wafer foundry is extending from the product level to the strategic level.

SK Group Chairman Chey Tae-won held a meeting with TSMC Chairman C.C. Wei on the 4th, the first such meeting between them since June 2024. According to SK Hynix’s official X account, the meeting focused on three major topics: next-generation AI technology, HBM, and advanced packaging.

The strategic background of this meeting is particularly noteworthy: starting from HBM4, SK Hynix has fully outsourced substrate chip production to TSMC, ending the traditional model of self-producing substrate chips for each generation of HBM. Reportedly, this shift is driven by the growing demand from AI customers for customizing substrate chip functionality, as well as TSMC’s process advantage in achieving fine-functional features with advanced manufacturing.

Meanwhile, as CoWoS—the core process for AI chip packaging—continues to face capacity constraints, TSMC’s pivotal role in the AI supply chain becomes increasingly prominent. Against this backdrop, SK Hynix is both deepening its packaging collaboration with TSMC and actively exploring advanced packaging cooperation with Intel to pursue diversified strategies.

Substrate Chip Outsourcing to TSMC, HBM Supply Chain Landscape Shifts

Reports indicate TSMC’s role in SK Hynix’s HBM strategy has fundamentally changed. For HBM3E and previous generations, SK Hynix produced substrate chips in-house; starting from the sixth generation, HBM4, this process has now been officially outsourced to TSMC. Specifically, HBM4 will use substrate chips manufactured with TSMC’s 12nm process technology and combine them with SK Hynix’s fifth-generation 10nm-class (1b) DRAM process, powering NVIDIA’s next-generation Vera Rubin platform.

This shift is attributed to rising demands for customization of substrate chip functions from clients, with TSMC’s advanced manufacturing meeting more refined functionality requirements. Competitive dynamics are also motivating factors: March media reports noted SK Hynix is considering using TSMC’s 3nm process for HBM4E’s logic substrate chips, partly to counter the pressure from Samsung’s plans to use its own 4nm process for HBM4E logic substrate chips.

CoWoS Capacity Shortfall, Advanced Packaging Becomes New AI Bottleneck

Advanced packaging has become another key bottleneck in the AI era and featured as an important agenda item at the meeting. According to reports, SK Hynix currently has a tight three-way collaborative framework with NVIDIA and TSMC: HBM supply is based on NVIDIA orders, while advanced packaging is handled by TSMC. However, analysis points out that the CoWoS process, which integrates GPU and HBM into a single package, currently cannot keep pace with surging demand.

TSMC’s monthly CoWoS output is expected to expand to about 115,000–140,000 units by the end of 2026, and further increase to around 170,000 units by 2027. Despite this, supply shortages persist. Reports say SK Hynix is also evaluating advanced packaging cooperation with Intel, and is already testing the feasibility of Intel’s 2.5D packaging solution based on EMIB technology in HBM applications—responding to potential supply risks arising from sustained CoWoS capacity pressure at TSMC.

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