AI computing power bottleneck easing? Report: TSMC CoWoS shortage to drop from 20% to 10%

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TSMC's advanced packaging capacity continues to expand, and bottlenecks in the AI chip supply chain are expected to gradually ease.

According to media reports citing institutional investors' views, as TSMC and its partners actively expand advanced packaging capacity, the supply-demand gap for CoWoS is expected to shrink significantly from the current 20% to around 10% by the end of 2026, and may further improve in 2027. This progress has a direct impact on the AI accelerator supply chain that relies on CoWoS packaging technology.

Meanwhile, TSMC is advancing the development layout for the next-generation packaging platform CoPoS (Chip-on-Panel-on-Substrate), NVIDIA's Feynman platform is expected to become one of the first clients to adopt this technology, with mass production planned for 2028 to 2029.

Faster capacity expansion, accelerated narrowing of supply-demand gap

According to TrendForce, TSMC's monthly CoWoS capacity is expected to reach 120,000 to 140,000 wafers by 2026, a record high. Including the additional 50,000 to 60,000 wafers of monthly capacity from outsourced assembly and test (OSAT) partners, the industry's total monthly capacity may reach nearly 200,000 wafers.

TrendForce predicts that the severe shortage of global 2.5D packaging capacity will begin to ease in 2027, supported by factors such as spillover effects from orders and TSMC's plan to expand CoWoS capacity by more than 60% in 2027.

Reuters reported that at TSMC's technology symposium held in May this year, TSMC forecasted that CoWoS advanced packaging capacity will achieve a compound annual growth rate of over 80% between 2022 and 2027, further proving the scale and intensity of this round of capacity expansion.

Next-generation CoPoS platform accelerates implementation, NVIDIA expected to be first adopter

While continuously expanding existing CoWoS capacity, TSMC is also paving the way for the next-generation advanced packaging platform, CoPoS. As wafer sizes continue to grow, CoPoS is seen as the key path to breakthrough current technology limitations.

TSMC established a CoPoS R&D production line at its subsidiary VisEra in 2025, with materials and equipment certification expected to be completed as early as June 2026, and pilot mass production targeted for mid-2027.

According to TrendForce, NVIDIA's Feynman platform is expected to be the first commercial client to adopt CoPoS technology, with the platform expected to enter full-scale mass production between 2028 and 2029, mainly deployed at TSMC's Chiayi site and its wafer fab in Arizona, USA.

Market significance: Key bottlenecks in the AI supply chain may be loosening

CoWoS packaging technology is a core process for current high-end AI accelerator production; its capacity tightness directly affects the shipping pace and delivery cycle of downstream AI chips. Shrinking the supply-demand gap from 20% to 10% means that the previously critical bottleneck limiting the expansion of AI hardware computing power is easing, helping reduce market concerns about AI infrastructure supply.

Over a longer cycle, the advance of the CoPoS platform supports TSMC in building a deeper technological moat in advanced packaging, and will further strengthen its core position in the AI chip supply chain.

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