CoWoS capacity support, JPMorgan raises TPU forecast again: shipments expected to reach 3.7 million and 5 million units this year and next year.
J.P. Morgan has once again raised its shipment forecast for Google's TPU chips, expecting shipments to reach 3.7 million and 5 million units in 2026 and 2027 respectively, mainly benefiting from TSMC's continued expansion of CoWoS packaging capacity and strong market demand.
According to ChaseWind Trading Desk, the analyst team led by Gokul Hariharan at the bank released a latest research report, raising the 2026 and 2027 CoWoS capacity forecasts by 8% and 13% respectively to reflect TSMC's new capacity ramp in the second half of 2026 and in 2027. TSMC's CoWoS capacity is expected to reach 115,000 wafers/month by the end of 2026, with external suppliers (mainly ASE Technology and Amkor) providing an additional 12,000 to 15,000 wafers/month. This is the bank's second upward revision of CoWoS capacity in three months.
J.P. Morgan pointed out, the increase in capacity mainly comes from rising demand in the ASIC supply chain. TSMC's expansion focuses on CoWoS-L technology, with part of its 65nm frontend capacity (Fab 14 and Fab 12) beginning to be used for LSI/interposer manufacturing, while CoWoS-S supply will remain basically stable, and CoWoS-R will be increasingly outsourced to packaging and testing houses such as ASE.

Strong TPU Demand Drives Up Capacity Forecasts
Based on strong demand signals from both the backend and frontend supply chains, J.P. Morgan has again raised Google's TPU shipment forecast. Analysts expect TPU shipments in 2026 and 2027 to reach 3.7 million and 5 million units respectively, higher than previous predictions.
To meet TPU demand, J.P. Morgan raised Broadcom's CoWoS wafer allocation to 230,000 wafers in 2026 and 350,000 wafers in 2027. For MediaTek, the allocation is expected to be 18,000 wafers in 2026 and 55,000 wafers in 2027. TPU v7 (Ironwood) and v8 series (Broadcom’s AX version and MediaTek’s X version) will account for most shipments during 2026-2027.
Currently, all TPU capacity is handled by TSMC’s CoWoS-S technology. Although certification of Amkor and ASE is underway to meet rising demand, progress is slow because TSMC is unlikely to expand CoWoS-S capacity, and J.P. Morgan expects packaging and test houses will not have significant TPU shipments in 2026. The v9 series TPU based on 2nm process is expected to start small batch production in cooperation with Broadcom by the end of 2027. This chip will use 3D SoIC packaging and CoWoS-L technology, with high technical complexity.
Nvidia Allocation Holds Steady, AMD and AWS Projects Progress Varies
J.P. Morgan maintains Nvidia's 2026 CoWoS allocation at 700,000 wafers, but with minor product mix adjustments. Due to HBM4 readiness issues, mass production of the Rubin series is delayed by 1-2 months, with corresponding shipment volume slightly reduced, while shipments of GB300 increase. Analysts expect Amkor to package about 400,000 to 500,000 H200 chips in 2026.
For 2027, J.P. Morgan raised Nvidia’s CoWoS allocation by 4% to reflect stronger demand for Rubin and Rubin Ultra series. TSMC will handle all CoW processes for Nvidia GPUs, while substrate parts will be outsourced to ASE. The Vera CPU project will start with TSMC’s CoWoS-R, but is expected to transfer to Amkor or ASE at the end of 2026 or start of 2027.
AMD's CoWoS forecast remains basically unchanged, with 90,000 wafers in 2026 and 120,000 in 2027, but shipments in 2026 are highly concentrated in Q4 (55,000 to 60,000 wafers), mainly because mass production of MI450 will begin around August–September. Considering this project faces multiple challenges, including Serdes, SoIC yield, ultra-large package size and rack-level integration, there is a risk of delay into 2027.
AWS's Trainium project is slightly adjusted down due to timing, with expected shipment of 2.1 million chips in 2026 (1.5 million Trn3 chips and 600,000 Trn2 chips), but the overall lifecycle volume remains unchanged. J.P. Morgan’s supply chain survey shows only CoWoS wafers led by Alchip and Annapurna are currently visible, while Marvell-led projects have not yet entered mass production.
Outsourcing Ratio to Packaging Plants Rises, Equipment Vendors Will Benefit
With TSMC CoWoS capacity severely constrained despite rapid growth, TSMC will focus on supporting key GPU and AI ASIC projects, leaving smaller or secondary projects to packaging houses. J.P. Morgan expects ASE to benefit by the end of 2026 and into 2027 from AMD Venice CPU, Nvidia Vera CPU, and parts of Trainium3 and TPU projects, continuing as a key outsourcing partner for TSMC’s substrate and wafer probe processes.
Amkor is expected to see incremental gains from Nvidia H200, Broadcom networking chips, Vera CPU, and eventually from portions of TPU orders. J.P. Morgan forecasts packaging and test houses will provide about 12,000 to 15,000 wafers/month of effective CoW capacity by the end of 2026. Intel’s EMIB-T technology is also being considered for some projects, including small-batch 2027 TPU projects for MediaTek and Broadcom.
J.P. Morgan believes strong demand for CoWoS, WMCM and FOCoS provides clear visibility through 2026 for Taiwan’s advanced packaging equipment suppliers (including Grand Process Technology, Scientech, All Ring, etc.). Equipment vendors expect CoWoS demand to grow year over year, with new capacity about 40,000 to 50,000 wafers/month, higher than about 35,000 wafers/month in 2025. Analysts expect equipment shipments by these vendors in 2026 could grow 20-30% year on year, or even higher.
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The above highlights are from ChaseWind Trading Desk.
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