"Disrupting" HBM? Intel XBM patent revealed: focuses on low packaging cost

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Intel is seeking to challenge the dominance of High Bandwidth Memory (HBM) with a completely new memory architecture, but commercialization remains a distant prospect.

Last week, Intel unveiled a patent application detailing its “Cross Batch Memory” (XBM) architecture solution. This design aims to bypass the current HBM dependence on silicon interposers, replacing traditional DRAM and its ultra-wide interface with backend process transistors and serial UCIe interconnect, thereby significantly reducing packaging costs.

According to Wccftech, XBM’s commercialization is targeted for post-2030, aligning with the timeline for the ZAM memory architecture co-developed by Intel and SAIMEMORY, a SoftBank subsidiary.

The HBM market is currently dominated by Korean manufacturers, with tight supply and high costs driving the search for alternatives. Intel’s patent disclosure adds a new variable to this competitive landscape, but analysts point out that ecosystem barriers and platform compatibility issues will be major obstacles for XBM’s market entry.

XBM Architecture: Replacing Wide Parallel Interface with Serial UCIe Interconnect

According to the patent, the core of the XBM architecture connects DRAM modules to a UCIe I/O module operating at 32 GT/s, with I/O signals routed through a base die.

Each XBM stack has a per-chip capacity ranging from 0.5GB to 5GB; each sub-channel consists of 12 data modules. An 8-layer XBM stack can accommodate up to 96 data modules, a 16-layer stack up to 192, with channel operating frequency at 2GHz.

In packaging form, XBM supports various configurations, including Memory-on-Package (MoP), enabling higher bandwidth and capacity in a smaller form factor. This flexibility is seen as one potential advantage of XBM over current HBM solutions.

Backend DRAM Process: Improved Area Efficiency and TSV Density

The key innovation at the process level for XBM lies in its use of a 1T1C (one transistor, one capacitor) backend DRAM structure.

According to Wccftech, this solution manufactures transistors in the backend metal layer (BEOL) rather than the front-end silicon substrate, greatly enhancing area efficiency and freeing up space for through-silicon vias (TSV), thus achieving higher memory density and bandwidth.

This design directly addresses core pain points of current HBM. According to an analysis by TrendForce cited in Global Economic News, traditional HBM requires micro-bump processes for vertically stacked DRAM chips, which drives up manufacturing costs, and silicon interposers further increase wiring complexity and overall expense. XBM’s architecture was proposed specifically to resolve these limitations.

SK Hynix and Samsung’s First-Mover Advantage Hard to Shake

Despite XBM’s technical appeal, its impact on the current competitive landscape is in question.

Global Economic News notes that SK Hynix and Samsung Electronics have been developing cost-saving technologies such as standard chiplets, UCIe, and fan-out packaging for years, giving them substantial first-mover advantages in cost optimization.

The key obstacle lies within the ecosystem. The global AI accelerator ecosystem centered on NVIDIA is highly adapted to current HBM architectures and their wide parallel interfaces. Migrating to an alternative memory architecture faces high platform compatibility and software adaptation costs. This means that, even if XBM is technically competitive, large-scale commercialization will require overcoming substantial industry inertia.

XBM’s commercialization window is expected post-2030, which means that for the foreseeable future, HBM will remain the mainstream solution for AI chip high-bandwidth memory demands. Intel’s patent represents an exploration of a technological direction, rather than an immediate disruption to the current market landscape.

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