From CoWoS to CoPoS, TSMC’s glass substrate validation breaks through packaging performance bottleneck

From CoWoS to CoPoS, TSMC’s glass substrate validation breaks through packaging performance bottleneck

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AI chips are getting bigger and bigger, and the ceiling for packaging materials is being redefined.

According to a Digitimes report on June 16th, TSMC recently publicly disclosed the progress of its "glass substrate" technology application for the first time, confirming that it is collaborating with ABF substrate giant Ibiden and panel manufacturer Innolux to jointly verify the feasibility of glass substrates for the next-generation CoWoS advanced packaging.

Meanwhile, TSMC also revealed that the competition in advanced packaging is gradually shifting from CoWoS to the CoPoS (Chip-on-Panel-on-Substrate) arena, and that it is working ahead of schedule to establish a complete ecosystem. According to supply chain sources, customer requirements for technical specifications and capacity, as well as growing pressure from competitors like Intel and Samsung, are causing the usually "cautious and not aggressive" TSMC to accelerate its pace of technological adoption.

Data Speaks: Performance Advantages of Glass Substrates in Large Packaging

TSMC's test sample used a 0.8mm glass core substrate, with packaging specs of 5x Reticle CoW, and an overall package size of 85×110mm, belonging to large-scale AI GPU packaging.

Validation results show significant improvement in several key metrics compared to organic substrates:

  • Package Warpage (COP) improved by 16%: Flatness of the package directly affects yield. As AI GPU sizes continue to grow (such as NVIDIA GB200, GB300 and the Rubin platform entering mass production), the importance of warpage control rises significantly.
  • Effective Thermal Expansion Coefficient (Effective CTE) decreased by 19%: The thermal expansion coefficient of glass is closer to that of silicon chips, resulting in less stress from temperature changes and helping reduce cracks and solder fatigue.
  • Effective Modulus increased by 31%: The substrate is more rigid, which is critical for large packages with increasing numbers of HBM stacks.
  • Power Integrity: Resistance decreased by 27%, inductance decreased by 42%, leading to significant improvement in power efficiency.

TSMC specifically emphasized that during testing, "no serious warpage or delamination/peeling issues" (No SeWaRe & Delamination) appeared—these two types of issues have always been major yield killers for large packaging.

"Thinner but Better": Glass Substrates Directly Challenge Organic Substrates

TSMC directly provided a qualitative comparison of the two substrates in this validation: Glass-SBT can be "thinner but with better COP," while Organic-SBT is "thicker but with worse COP."

In other words, glass substrates can not only be made thinner, but their package flatness and reliability are even superior. This conclusion has direct technological substitution significance for the AI chip market pursuing high-density, large-sized packaging.

However, TSMC also clearly stated that further research on optimizing glass thickness and large-scale CoWoS package layout is still necessary, and widespread mass production is still some distance away.

Glass Itself Isn't the Hardest Part—It's Making the Vias

The core technical challenge for glass substrates is the Through Glass Via (TGV).

Glass is essentially an insulator and must use tens of thousands of TGVs to create vertical conductive vias that enable signal and power transmission. But glass also has high hardness and brittleness, which makes micro-cracks easy to form during processing and affects reliability and yield.

Via formation, copper filling quality, and long-term thermal reliability are considered the three core hurdles for glass substrates to reach mass production.

Supply Chain Layout: Why Ibiden and Innolux Got Involved

The list of partners in this collaboration itself reveals the direction of supply chain layout.

Ibiden is currently a major substrate supplier for NVIDIA and AMD AI chips, and has previously announced an investment of 500 billion yen to expand its Ohno factory in Gifu Prefecture, specializing in advanced substrates for AI servers. Its inclusion by TSMC in glass substrate validation further confirms its central role in the next-generation packaging supply chain.

Innolux's involvement is seen by industry as a significant development for panel manufacturers entering the glass substrate track. Panel makers have established capabilities in large-size glass processing, and their cooperation with TSMC may open up new business areas.

Competitive Pressure: Intel and Samsung Are Already Ahead

TSMC's acceleration is clearly driven by competitive pressure.

Intel has been working on glass substrates for over ten years and is the earliest and most deeply invested entrant globally. Its glass substrate pilot line in Arizona in the US is gradually entering commercialization, aiming to combine glass substrates with ultra-large chiplet packaging to win AI GPU and ASIC customer orders.

Samsung Electro-Mechanics (Semco) will set up a glass substrate pilot line in 2025, and has established a joint venture with Japan's Sumitomo Chemical Group to build the glass substrate supply chain ahead of time.

By comparison, this is TSMC's first public disclosure of its glass substrate validation results. In terms of timeline, TSMC's public move comes later than Intel and Samsung, but its tripartite validation with Ibiden and Innolux, as well as its direct integration with the CoWoS/CoPoS packaging platform, show it is advancing quickly on its own timeline.

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