Huawei has changed the way semiconductors are measured.

Author | Link Editor | Song He There is an open secret in the semiconductor industry: Moore's Law is approaching its limit. This is an accepted fact in the industry. For the past 60 years, from Intel, TSMC to ASML, the underlying rule that keeps the entire industry chain running is being challenged. Today, the most advanced nanometer-level chip gate width is only a dozen silicon atoms wide. Any smaller, due to quantum tunneling effects, electrons will no longer be effectively constrained by semiconductors. This path of continuously shrinking the process has been going on for sixty years. Everyone knows where the end is, but no one is willing to admit it publicly. Until May 25, 2026, He Tingbo, Huawei company director and president of the semiconductor business unit, announced a new principle for semiconductor evolution: Tao (τ) Law, whose core proposition is to replace "geometric scaling" of Moore's Law with "temporal scaling". As Moore's Law approaches its limit, He Tingbo believes a new path is worth exploring: namely, no longer focusing on shrinking transistors, but making signals run faster. Based on this path, Huawei has mass-produced 381 chips in the past six years. The new generation Kirin chip to be released this autumn will achieve more than a 50% increase in transistor density without changing the process. By 2031, Huawei plans for its chip transistor density to match the level of the 1.4 nm process, using this methodology. In fact, Tao Law did not emerge out of thin air. From Nvidia to TSMC, from AMD to SK Hynix, the entire semiconductor industry has been exploring this direction for nearly ten years. Huawei's statement this time formally outlines a clear framework and standard for this exploration for the first time. I. The End of the Old Road τ (tau) is known as the "time constant" in circuit theory. There are billions of transistors in a chip, connected by metal wires. Signals run along the wires, but wires have resistance. The longer the wire, the greater the resistance, and the slower the signal. Therefore, the smaller the τ, the faster the signal, and the stronger the chip performance. The process of shrinking transistors over the past decades has essentially not only increased transistor density, but also synchronously reduced parasitic capacitance and signal transmission delay, so the RC time constant has been declining for a long time. The idea of Tao Law is imbued with first principles thinking: since the goal is to reduce τ to improve efficiency, besides making transistors smaller, obviously compression can also be achieved in other dimensions. He Tingbo breaks τ into four layers: transistor layer, circuit layer, chip layer, system layer, each with different methods to compress time. The reason Tao Law must resolutely pursue this new path is because the old path has reached its end. In 1965, Gordon Moore put forth the prediction that the number of transistors in an integrated circuit would double every two years. Moore’s Law has become both an industry rule and a consensus. Everyone developed, invested, and built plants according to this pace, ultimately making the prediction self-fulfilling. It initially had a perfect partner: Dennard scaling, meaning that as transistors shrank, power density remained unchanged, implying that chips were not only faster but heat was controllable. Stacked together, the two laws constituted the foundational faith of the information industry for half a century. From design and manufacturing to equipment and materials, the entire industry chain ran on the same track. Nanometer-level advanced processes gradually became the coordinates of power in the industry; the company able to produce the most advanced chips was more likely to be at the top of the food chain. Dennard scaling fell first around 2005; people found that when the size was too small, the heat of chips became uncontrollable, so Intel abandoned frequency scaling and began shifting to multicore designs. The rise of the smartphone era indeed prolonged Moore's Law. But after entering the single-digit nanometer era, every step of scaling resulted in exponential increases in cost and difficulty. Building a 3 nm wafer fab costs upwards of billions of dollars; there are now only a handful of players globally who can afford it. He Tingbo put it bluntly in her paper: After 7 nanometers, the returns from pure size reduction have flattened out. As advanced processes enter the deep end, interconnect delay, power consumption, and data transfer costs account for a growing portion of system performance, and the rising cost from relying only on advanced processes is increasingly uncontrollable. Thus, the core promise that has supported the industry for the past half-century — "using lower costs to produce more transistors in each generation" — can no longer be kept. II. How Industry Players Break Through Heavyweights in the industry have all attempted breakthroughs in this direction. The earliest and most aggressive is Nvidia's cluster expansion. In 2016, Nvidia introduced the high-speed interconnect bus NVLink between GPUs on Pascal architecture's P100. What Jensen Huang wanted to solve was the data transmission bottleneck between GPUs. Looking back ten years later, the bet was precise. From the first generation NVLink to the fifth generation in the 2024 Blackwell architecture, inter-GPU bandwidth has increased dozens of times. GB200 NVL72 uses fifth generation NVLink to connect 72 GPUs into one unit; individual GPU bi-directional bandwidth is 1.8TB/s, and total NVLink domain bandwidth exceeds 130TB/s. Nvidia even uses NVLink-C2C to directly solder GPU and CPU together, sharing unified memory space. At the first launch event, Jensen Huang was more willing to talk about "interconnect" rather than just "compute power". AMD took another route. In 2019, Zen 2 began manufacturing processors as multiple small chips and then packaging them together, aimed at breaking photomask limits and stabilizing yields. This Chiplet concept went further in AI chips: at the end of 2023, the MI300X used TSMC's 3D packaging technology to vertically stack multiple compute dies and IO dies, integrating 153 billion transistors and 192GB of HBM3 memory in a single package. AMD no longer fixates on advanced processes, but achieves integration at the packaging level that single chips could not reach before, using the "build separately, use together" approach. TSMC’s shift is also obvious. For many years, TSMC's advanced process narrative was simply going smaller—from 5nm to 3nm, 2nm, all the way down. But from 2023 on, advanced packaging quickly took up more of TSMC's capex and strategic narrative. CoWoS packaging technology, targeting bandwidth density, attaches GPU chips and HBM memory together; its production has long been in short supply and is a critical step in AI chip shipments. At the 2026 technology forum, TSMC released a "three-layer cake" AI platform architecture: the base is computing, the middle is integrated packaging, and the top is photonic interconnect. The COUPE technology at the top replaces electric signals with optical signals for chip-to-chip transmission, boosting energy efficiency several times and reducing latency by an order of magnitude. The king of process now tells the story of packaging and light. Memory manufacturers' arms race is even more intense. SK Hynix and Samsung compete around HBM, aiming to bring memory closer to computing and feed data faster. From HBM2 to HBM3 and HBM3E, each generation stacks memory chips higher and binds them closer to GPUs. Next-gen HBM4 will introduce hybrid bonding technology, no longer needing solder bumps; copper-to-copper connects directly at the atomic level, boosting interconnect density by one or two orders of magnitude. Additionally, there is Intel’s Foveros 3D packaging, the industry-driven UCIe chiplet interconnect standard, and accelerating industrialization of silicon photonics. The entire industry is actually adjusting direction, challenging a common goal: When transistors can't shrink further, make data run faster. Over the past decade, R&D focus shifted from "making smaller switches" to "building faster highways". III. Huawei's Strengths and Position In this industry-wide breakthrough, Huawei stands in a very special position. Constraints on advanced lithography equipment have made Huawei confront the issue earlier and more urgently than others: if process scaling becomes an obstacle, how can engineering design achieve target efficiency? But this is instead a field in which Huawei, rooted in communications, holds advantages. From program-controlled switches to 5G base stations, organizing numerous scattered nodes into a coordinated system has been one of Huawei's core strengths accumulated over decades. As AI-era data centers increasingly resemble super-large communication networks, Huawei's strengths suddenly gain new strategic value. In the four-layer optimization system, the entry point at the device layer is also to optimize the resistance of wires around transistors, compressing signal delay from the physical layer. At the circuit layer, Huawei adopts a method called Logic Folding. Traditional chip circuits are laid out on a plane; signals detour left and right, and longer traces slow them down. Logic folding unfolds the circuit into two layers, like folding a piece of paper, so signal paths that used to run across horizontally now go straight vertically. Actual data for Kirin 2026: single-generation transistor density increased by over 50%, energy efficiency improved 41%, CPU frequency restored to 3.1GHz, cache frequency up over 40%, core line length cut by about 30%. Plans for three-layer and four-layer folding aim for frequency above 4GHz by 2029. This is similar in concept to AMD's 3D chip stacking or Intel's Foveros methodology—all move from planar to three-dimensional. The difference is that AMD and Intel stack multiple different chips vertically, while Huawei folds the internal circuits of a single chip. At the chip layer, Huawei synchronizes software, architecture, and chips. That is, allocate internal chip resources based on actual task requirements, cutting out all unnecessary waiting. Just as Nvidia deeply coordinates in its CUDA ecosystem, and AMD pushes ROCm, these are different solutions to the same problem. The system layer may be where Huawei’s unique genetics shine most. Lingqu bus was initiated in 2019 and released six years later, using a unified protocol to replace the stacked communication protocol layers in AI clusters. Actual results show system communication latency dropping from tens of microseconds to about 100 nanoseconds, a nearly 500-fold reduction. On top of Lingqu, the Hi-ONE optical interconnect engine replaces copper for data transmission, offering 8Tb/s of bandwidth per module and extending transmission distance from less than 1 meter to 100 meters. Compared to Nvidia: Nvidia solves interconnect problems with layered combinations of NVLink + NVSwitch + InfiniBand; Huawei’s Lingqu idea is to use one protocol to connect all layers. Nvidia's GB200 NVL72 connects 72 GPUs into one unit, Huawei's Atlas 960 SuperPod uses Lingqu to connect 15,488 Ascend cards into a super node. Both companies, starting from their respective technologies, are reaching the same destination: making tens of thousands of cards work together as one machine. He Tingbo’s own experience is also a microcosm of Huawei’s chip destiny. She joined Huawei in 1996 to work on optical communication chips, went alone to Shanghai in 1998 to build a 3G chip team, later worked two years in Silicon Valley, and has long led HiSilicon. During the supply chain crisis in 2019, it was He Tingbo who issued the famous "plan B becomes plan A" internal note. She is both the soul of Huawei’s chip business and the one most deeply affected by process limitation pains. In a certain sense, Tao Law is also a product of this pressure. IV. System and Chain Reconstruction What Tao Law does is to define in a more systematic way the industry-wide shift of recent years. Nvidia invested a decade in NVLink, solving the system-level τ. TSMC developed CoWoS and 3D packaging, solving circuit and chip-level τ. SK Hynix works on HBM, solving memory and compute τ. AMD pushed Chiplet, solving chip-to-chip communication τ. Each company compresses time from its own angle, but previously no one integrated these efforts into a unified coordinates for system-level integration and narrative. The uniqueness of Huawei’s Tao Law is that it establishes this coordinate system. He Tingbo wrote something weighty in her paper: τ scaling is the first scaling principle after Dennard Law to establish a shared optimization goal across the entire computing stack. As Moore’s Law’s role as a unified coordinate system wanes, the whole industry truly needs a new yardstick. For the past sixty years, semiconductor progress measuring sticks have mostly looked at nanometer-level process. This stick is simple and powerful, but measures what is essentially a non-first-principle proxy indicator—shrinking transistors is not the goal itself; higher compute density and shorter signal propagation time are. But now this yardstick can't shrink anymore. Changing the measuring stick means redistribution of discourse power. Previously, those at the top of the food chain were companies with the most advanced processes. But in the dimension of "temporal scaling", packaging factories, memory companies, interconnect protocol designers, and system architects may all participate in a game that used to be exclusive to the frontier of processes. TSMC's advanced process still has irreplaceable value, but Tao Law turns it from the only choice into one of many possible options. He Tingbo concludes: "The future belongs to open cooperation. No company can solve all the answers alone on the path of semiconductor evolution." As with user co-creation in the CUDA ecosystem, the construction of Tao Law also needs an ecosystem. Just as Nvidia needs TSMC’s packaging, TSMC needs SK Hynix’s HBM, SK Hynix needs yield breakthroughs from hybrid bonding equipment makers, Huawei's Lingqu needs a rich supply chain of optical modules, and so forth. The four-layer optimization system described by Tao Law sees each layer belonging to different industry segments, and this will drive another reconstruction of the semiconductor industry chain. For the past sixty years, the core of competition in the semiconductor industry was who could achieve the next nanometer first. This race shaped the careers of several generations of engineers and determined the flow of trillions of dollars in capital. Now the validity period of that phrase is expiring, replaced by a new key question: Who can save one nanosecond for signal travel. Previously, we measured space; now, we measure time. It may sound like only a change of unit, but the last time the semiconductor industry switched measurement standards was in 1965. Behind this is bound to be the rearrangement of power, profits, and rules throughout the entire industry chain. This rearrangement won't happen overnight, but the direction is already irreversible. Risk disclaimer and terms Market risks exist, investment must be prudent. This article does not constitute personal investment advice, nor does it consider the unique investment goals, financial situation, or needs of individual users. Users should assess whether any opinions, views, or conclusions in this article suit their specific circumstances. Invest accordingly, at your own risk.