Huawei Tau Law Shockwave: The Race Point for Chips is Shifting
The chip market landscape may be on the verge of a sudden upheaval.
On May 25, 2026, He Tingbo, President of Huawei’s Semiconductor Business Unit, introduced a new concept: “Tao (τ) Law,” sparking waves across the industry. As Moore’s Law reaches its limits, Huawei appears to have found a “curve-saving-the-country” solution.
For the past 60 years, the global semiconductor industry has followed Moore's Law, racing to finer process nodes—transistors got smaller, performance grew stronger, costs fell lower. It powered PCs, smartphones, and the internet. More importantly, it established a stable expectation for the industry. Chip companies knew how much performance the next generation would improve; equipment makers knew where the next process would head.
In some sense, Moore’s Law is like a “time order” in the semiconductor world. But in recent years, cracks have begun to appear. Beyond 7nm, the progression of advanced processes significantly slowed. EUV lithography machine prices kept climbing, mask costs rose, and design complexity began to grow exponentially.
Design budgets for a single 2nm chip have already surpassed $1 billion, and per-transistor costs at advanced nodes are even starting to reverse and rise. The industry assumption that “more advanced processes mean lower cost” is gradually failing.
Huawei’s solution is to switch tracks. He Tingbo explained, previously everyone competed to “make the road as narrow as possible”—shrinking lanes so more cars could fit. But when the lane becomes as narrow as the car itself, cars start to “spill out.”
Tao Law no longer races to narrow the lanes, but to make signals run faster and smoother. The new law is to turn single-story houses into skyscrapers—signals that once had to traverse kilometers can now reach their destination by elevator. Huawei has named this vertically stacked core technology “logic folding.”
Industry observers wonder: as this disruptive story is unveiled, if it’s accepted, who will reshuffle, and who will gain the advantage?
Side Characters Step into the Spotlight
For the past thirty years, semiconductor industry profit distribution followed a clear food chain: whoever controls the most advanced lithography machines and fabs takes the biggest slice of cake.
TSMC grabs the thickest profits, ASML rules the globe with a single EUV lithography machine, while Samsung and Intel burn astronomical amounts in pursuit. Packaging, interconnects, substrate materials, EDA—these have long been seen as “supporting roles,” with lower valuations and influence.
The subtext of Tao Law is that this hierarchy needs to change. If performance no longer hinges solely on process node nanometers, but on how smoothly signals run inside chips, how tightly they stack, how fast they interconnect, then what determines a chip’s performance shifts from lithography precision to how well chips are stacked. This means the value of packaging could be entirely reconsidered.
The most direct beneficiary will be advanced packaging.
TSMC’s CoWoS and SoIC, Samsung’s X-Cube, Intel’s Foveros—these abilities, once classified as “packaging technology,” are rapidly approaching the strategic importance of processes themselves. TSMC’s CoWoS capacity continues to expand from 2024 to 2026 but is still in short supply, forcing Nvidia to partner with multiple packaging factories—a clear sign the industry is voting with its feet.
Domestically, firms once only earning processing fees within the global packaging and testing chain can now touch high value-added segments. As demand for Chiplet (small chips) and 2.5D/3D stacking surges, packaging enterprises’ capital expenditures and profit models may be collectively reassessed.
Next at center stage are interconnects and bandwidth. He Tingbo repeatedly mentioned “Lingqu Bus” and optical interconnects—the real core is the “highway network” inside and between chips.
Once computing power is sufficiently stacked, delays and energy consumption in data transfer become bottlenecks. In AI large model training, over half the energy is spent moving data, not in computation itself.
This is why HBM high-bandwidth memory has recently become a money printer for SK Hynix, Samsung, and Micron; and why Nvidia’s NVLink and NVSwitch are more important than raw single-card computing power.
Under the guidance of Tao Law, at least half of future chip competitiveness will be in the “road,” not just the “car.”
On the materials side, it goes deeper. He Tingbo’s paper mentions, “If there is a breakthrough in materials science, using a material with a better dielectric constant, there will be room for improvement.”
In other words, low dielectric constant media, two-dimensional semiconductors, cobalt, ruthenium, even graphene as new interconnect metals—these previously “edge innovations” under Moore’s Law will be re-evaluated.
Domestic manufacturers making photoresist, wet electronic chemicals, or sputtering targets, if they break through in low-k media or new interconnect materials, can switch from catching up and substituting to globally synchronized R&D.
Opportunity to Shed Burdens
But all of this is built on one premise: Tao Law must truly achieve “universal economics.”
Moore's Law's influence lies in accompanying scalable economics for 60 years: per-transistor costs always decreased. Tao Law has not yet passed this comprehensive test.
Not all supply chain enterprises buy into this narrative.
A manager from an upstream semiconductor equipment company pointed out: “Currently, this theory has limited industry impact in the short term. But if advances push the process below 1nm, the industry will face challenges.”
In his view, Huawei’s technical plan is to match performance via architecture, algorithms, and other soft technologies given a lack of top lithography machines, but this mode cannot replace hardware-level technical breakthroughs.
A key question emerges: While 3D stacking and logic folding may work technically, when mass-producing millions or tens of millions of chips, can the economics of τshrinking still add up? These are questions industrialization must answer.
He Tingbo herself acknowledges this, saying, “The framework for the next decade’s technology development is clear, but many issues remain to be solved. No single company can overcome them. Tool chains, industry standards, performance benchmarks, device physics, business models—all require industry-wide collaboration.”
Huawei expresses willingness to open up access to the core Tao Law technology framework, logic folding IP, and Lingqu Bus protocol, and calls to establish a Tao Law industrial alliance.
In other words, if domestic packaging, materials, EDA, interconnect, and wafer manufacturers are willing to bet on this path together, Tao Law could turn from “Huawei’s technical narrative” into a true ecosystem-level opportunity for China’s semiconductor industry.
But He Tingbo left the capital market with a judgment: The next investment should follow τ, not just process node. Product competitiveness no longer depends entirely on cutting-edge lithography—chip packaging, memory bandwidth, interconnect architecture have reached the strategic status of advanced logic processes.
For investors, this means a shift in valuation framework: logic that previously gave high valuations to foundries may in future allocate more to packaging, interconnect, and materials companies.
In a sense, Tao Law isn't here to kill Moore's; it’s more like a second ruler handed to an industry at its bottleneck.
Whether this new ruler ultimately becomes a second pillar in semiconductor history, or is merely a dignified expression under microphysics constraints, may only be determined when the Kirin chip using logic folding technology is truly released in autumn 2026, with the market responding with sales and performance.
The game rules are changing; the seatings at the table will follow. A new post-Moore era story is just beginning.
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