Huawei’s "Tao’s Law" Reshapes the Semiconductor Narrative, Ushering in a New Boom Window for Advanced Packaging, Foundry, and Mature Process Technology

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After Huawei proposed the "Tao (τ) Law," the semiconductor investment narrative is shifting from purely pursuing geometric process miniaturization to "time scaling" and system-level collaborative optimization. The latest views from Guosheng Securities, Huatai Securities, and CITIC Securities all point to a consensus: advanced process, advanced packaging, equipment, EDA, CPO, and mature process may simultaneously enter a higher prosperity observation window.

According to People's Daily, He Tingbo, Huawei company director and president of the semiconductor business unit, delivered a keynote speech titled "Exploration and Practice of the New Path in Semiconductors" at IEEE ISCAS 2026 on May 25, 2026, and proposed a new principle to guide the development of the semiconductor industry—Tao (τ) Law. The core of this law is to continuously reduce the time constant τ through optimization at four levels: transistor, circuit, chip, and system.

All three brokerages believe that the key to this route is not to replace all advanced processes, but, in the context of Moore's Law slowing and rising geometric miniaturization costs, to provide another path for chip performance improvement. Huatai Securities interprets this as system technology collaborative optimization (STCO), an evolution of the methodology; CITIC Securities emphasizes compensation for short-term process node gaps through system topology optimization; Guosheng Securities puts more emphasis on its promotion of the Chinese semiconductor industry cycle and domestic substitution.

For the market, the direct impact may first be seen in two main lines: first, incremental demand brought by increased complexity in technologies such as advanced packaging, 3D integration, equipment, and EDA; second, AI server drives demand for supporting chips such as power management, analog, and networking, while some overseas mature capacity shrinks, leading to tighter supply and demand for mature processes. The consensus among brokerages is that the focus of semiconductor market attention is expanding from single advanced nodes to "resonance of advanced and mature processes".

Consensus: Shift from "geometric miniaturization" to "time scaling"

The three brokerages share a common starting point in their understanding of the Tao Law: geometric miniaturization, which traditional Moore's Law relies on, is facing cost and physical constraints.

Guosheng Securities points out that as processes approach the atomic level, the difficulty of shrinking transistors increases steeply, process costs rise exponentially, and the benefits of geometric miniaturization gradually fade. Meanwhile, the demand for computing power in areas such as AI and high-performance computing is rapidly increasing, and traditional processes cannot fully match industry needs.

CITIC Securities' description leans more to fundamental logic. It believes the essence of device miniaturization is to shorten signal transmission paths, with the fundamental goal of reducing system time. Therefore, Huawei proposed using the time constant τ as the metric and reducing latency at the four levels of transistor, circuit, chip, and system.

Huatai Securities interprets the "Tao Law" in the context of global semiconductor technology evolution. It claims that the law is essentially a further evolution of the STCO methodology, that is, through collaborative design of devices, circuits, chips, and systems, to achieve optimal system-wide performance. This aligns with the direction of mainstream chip companies’ exploration of system-level collaborative design globally.

Divergence: Guosheng focuses on cycles, Huatai on collaboration, CITIC on process

The three brokerages have different emphases.

Guosheng Securities emphasizes industrial cycles the most. It believes the release of the "Tao Law" is likely to accelerate the domestic technological development of advanced process and packaging industries and form a resonance with the reversal of supply and demand in mature processes. Guosheng maintains an "overweight" rating for the semiconductor industry and is optimistic about domestic manufacturing and equipment benefiting from technology breakthroughs and capacity expansion.

Huatai Securities puts more emphasis on the boundaries of the technology route. It claims that the "Tao Law" is highly compatible with global mainstream trends such as GAA, backside power supply BS-PDN, advanced packaging, and CPO, but it does not replace the High-NA EUV route promoted by ASML. Instead, they improve semiconductor performance from different dimensions. In other words, Huatai does not see it as a simple substitute for advanced lithography but as a supplement and extension of system-level optimization.

CITIC Securities offers the most detailed process breakdown. It divides the "Tao Law" into four layers: at the transistor level, it focuses on mobility enhancement, strain engineering, high-k metal gate, and GAA architecture; at the circuit level, it focuses on low-resistance conductors, low-k dielectrics, vertical integration, and logic folding; at the chip level, it focuses on 3D stacking and HBM; at the system level, it focuses on Unified Bus, near-packaged optical engine Hi-ONE, and interconnect architecture design.

Technical Line: Logic Folding Brings Advanced Packaging to the Forefront

"Logic folding" is a recurring key term in the three viewpoints.

Guosheng Securities says that Huawei proposed core technologies such as "logic folding," constructing a multi-level collaborative optimization system spanning devices, circuits, chips, and systems, compressing signal propagation delay and enhancing transistor density and system performance without relying on extreme physical processes. Guosheng also claims that over the past six years, Huawei designed and mass-produced 381 chips based on the Tao (τ) Law, covering multiple industry demands.

CITIC Securities further points out that Huawei will launch mobile SoC chips using logic folding technology in autumn 2026, achieving a 55% equivalent transistor density boost and a 41% improvement in energy efficiency at a fixed process node. It believes that achieving three-dimensional spatial topology reorganization relies on hybrid bonding and TSV processes.

Huatai Securities also believes that logic folding and 3D stacking will significantly increase process complexity, pushing the industry's technical focus toward the "Beyond Moore" framework. This means that advanced packaging is no longer just a supplementary post-processing segment but may become an important source of performance improvement.

Industry Chain Impact: Foundry, Equipment, EDA, and CPO Become Primary Beneficiaries

From an investment mapping perspective, all three brokerages prioritize leading local foundries.

Huatai Securities recommends focusing on local foundry leaders such as SMIC and Hua Hong Semiconductor, believing their advanced process lines based on DUV may play a role in Huawei's progression toward equivalent 1.4nm.

Guosheng Securities lists a broader range of beneficiaries, including semiconductor manufacturing, front-end equipment, back-end equipment, materials, and packaging & testing. Relevant companies include SMIC, Hua Hong, Jinghe Integration, Sinlian Integration; in front-end equipment: AMEC, NAURA, TJ Technologies, Huahai Qingke, Zhongke Flying Measurement; in packaging & testing: Shenghe Micro, JCET, Tongfu Microelectronic, Chipown Technology, Yongsil Electronics, etc.

Huatai Securities also notes that increasing process complexity may drive advanced packaging sectors, catalyzing demand for etching, thin-film, bonding, CMP, and other equipment, and driving EDA segment's full-process 3DIC tool demand. It mentions directions including Huada Jiutian, Empyrean, VeriSilicon, and high-bandwidth optical interconnect technologies like CPO.

Mature Process: AI Power Demand and Capacity Contraction Form the Second Main Line

Guosheng Securities makes an important judgment that mature processes may also enter a supply-demand reversal.

It points out that the power per rack of new-generation AI servers has risen from 3–5kW in regular servers to 15–20kW, with core chip power consumption exceeding 1400W, requiring several times more power management chips than regular servers. According to TrendForce, AI servers’ demand for power density far exceeds that of general-purpose servers, so the 8-inch wafer BCD process is now heavily tilted towards AI PMIC.

Supply is also contracting. Guosheng notes that TSMC will gradually reduce 8-inch capacity starting in 2025, planning for partial plant-wide halts by 2027, concentrating resources onto advanced process and high-end packaging; Samsung foundry will contract 8-inch lines in the second half of 2025, shifting capacity and capital expenditure to 12-inch advanced processes.

Huatai Securities, in its views on SMIC and Hua Hong Semiconductor, also emphasizes that AI demand is driving growth in supporting chips such as power management, analog, and networking, and overseas foundries switching production is leading to reduced mature process foundry capacity. The combination may push foundry service ASP into a structurally upwards cycle.

Investors Need to Distinguish Three Timelines

Combining the three viewpoints, investors need to distinguish short-, mid-, and long-term logic.

In the short term, the market may first trade policy and technology narrative, as well as reevaluate foundry and packaging & testing chains due to tighter supply and demand for mature processes.

In the mid-term, if technologies like logic folding, hybrid bonding, TSV, 3D stacking, and CPO see larger-scale application, order elasticity in equipment, materials, advanced packaging, and EDA segments will be more worth tracking.

In the long term, the key still lies in technological realization. Guosheng Securities notes that the transistor density of high-end chips based on Tao (τ) Law is expected to reach the equivalent 1.4nm process level by 2031; Huatai Securities describes Huawei's goal as achieving chip efficiency equivalent to 1.4nm without EUV by 2031. CITIC Securities adds that for AI systems, relevant packaging topology reorganization technologies are expected to enable hardware integration more than 100 times larger than 2026 by 2035.

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