Intel's next-generation server chip Diamond Rapids debuts, betting on the era of AI Agents

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Intel officially showcased its next-generation server processor Diamond Rapids at Hot Chips 2026, highlighting up to 256 P-cores and an all-new Fan-out Fabric architecture as its core selling points, positioning the product for enterprise-level AI Agent infrastructure and directly confronting the increasingly fierce competition from AMD and Arm.

Diamond Rapids will be built using the Intel 18A-P process, supporting up to 1.6TB/s memory bandwidth, 128 PCIe Gen 6 lanes, and CXL 3.0, with a core count increase of over 50% compared to the previous-generation Xeon 6. Intel CEO Lix Wu has recently hinted that, due to the continuously rising CPU demand from AI Agent workloads, the subsequent product roadmap may be accelerated.

This debut comes at a time when the data center CPU market landscape is evolving rapidly. AMD’s EPYC Venice series also offers a 256-core “Zen 6” processor, while Nvidia is advancing a dual-route CPU layout for both x86 and Arm. Intel’s dominance in the server market is under pressure from multiple sides.

New Architecture: Fan-out Fabric Reshapes Chip Design

The most notable technological innovation of Diamond Rapids is Intel’s claim of being “the first CPU to use the Fan-out Fabric architecture.” This architecture divides chip functions into four major modules: Scalable Compute Building Blocks, Centralized I/O and Memory Fabric Hub, Unified Memory Fabric, and Flexible I/O Fabric.

Physically, the chip is composed of 22 independent dies, specifically including 16 core chiplets based on Intel 18A-P process, 2 Fabric Hubs based on Intel 3 process, and 4 Base Tiles based on Intel 3-T process, connected via Foveros Direct 3D hybrid bonding and UCIe-S copper interconnects. This design approach closely resembles that of AMD EPYC Venice, which uses multiple CPU chiplets surrounding a large I/O die.

A key difference from the previous Granite Rapids is that Diamond Rapids separates the memory controller from the compute chiplets and incorporates it into the Fabric Hub, allowing for more flexible scalability. Each Compute Building Block contains 16 cores and features a built-in 3D Xbar connecting cores to the last-level cache (LLC) on the Base Tiles. The entire chip shares a 1.28GB LLC, with each Base Tile providing 320MB.

Core Specs: 256 Cores Match AMD, Huge Leap in Memory Bandwidth

In terms of core count, Diamond Rapids offers up to 256 Panther Cove-X P-cores, organized in four groups of Compute Building Blocks each containing four core chiplets, doubling the maximum 128 cores of Xeon 6 and matching the upper limit of AMD EPYC Venice.

For memory subsystem, Diamond Rapids supports a 16-channel design, reaching up to 12800 MT/s with MRDIMMs, and 8000 MT/s with standard DDR5, with peak memory bandwidth up to 1.6TB/s. On I/O, the chip provides 128 PCIe Gen 6 lanes and supports CXL 3.0, offering ample expansion for storage and network-intensive scenarios. Additionally, the chip introduces a new Advanced Performance Extension (APX) and enhanced Advanced Matrix Extension (AMX) for accelerating AI inference and matrix operations.

Notably, Diamond Rapids does not support hyper-threading (SMT); this feature will return in the successor, Coral Rapids. For the platform, the chip uses the LGA 9324 socket and a maximum TDP of 650W.

Product Roadmap: Coral Rapids Accelerates, Custom Nvidia SKU Incoming

In terms of product planning, the next stop after Intel’s Diamond Rapids is Coral Rapids, expected to launch in mid-2028, which will reintroduce SMT support and use an 8-channel memory platform. Lix Wu recently stated that, given the fast-growing demand for general-purpose processors from AI Agent workloads, the timeline for this product line may be accelerated. Notably, Intel had previously planned an 8-channel version of Diamond Rapids but ultimately canceled it, focusing resources on the 16-channel version.

In terms of competition and cooperation, Intel is working with Nvidia on custom products, and a custom x86 SKU with NVLink interface is reportedly in development for Nvidia’s use. This move means Intel’s Xeon architecture will be directly integrated into Nvidia’s CPU diversification strategy, and Intel will compete head-on in the data center CPU market with Nvidia Vera and AMD Venice.

The core logic behind Intel’s bet is: In the era of AI Agents, the strategic value of general-purpose processors in AI infrastructure will rise again, opening larger market space for the Xeon series. Whether this holds true will largely depend on the mass production timeline and actual delivery performance of Diamond Rapids.

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