Interconnecting and pooling, breaking the memory wall—CXL: The core infrastructure of the AI computing era
```
The computing power demands of large AI models are exploding exponentially, but the speed at which computing chips evolve far outpaces the upgrade rhythm of memory systems. The “memory wall” has become the core bottleneck restricting the sustainable development of the AI industry. CXL (Compute Express Link) protocol, as the industry’s key solution to this bottleneck, is reaching a historic inflection point as it transitions from "technical exploration" to "large-scale commercial application."
The CXL industry is experiencing the superimposition and resonance of three logics: In the short term, the explosive demand for KV Cache in AI inference scenarios has created just-needed memory expansion, and CXL memory controllers have entered a period of rapid scaling; In the medium term, CXL Switch drives memory from "expansion" to "pooling," which will reconstruct the resource scheduling patterns of data centers; In the long term, technological breakthroughs such as CXL over Optics will enable inter-cabinet and inter-rack memory interconnection, opening up tens of billions of dollars in market space.
I. What’s Happening? The Memory Wall Strikes
The computing power demands of large AI models are exploding exponentially, but chip performance iterations far surpass the pace of memory system upgrades. The “memory wall” has become the core bottleneck restricting the sustainable development of the AI industry. The CXL (Compute Express Link) protocol, as the industry's key solution to breaking this bottleneck, is reaching a historic inflection point as it transitions from “technical exploration” to “large-scale commercial application.”
The CXL industry is experiencing the superimposition and resonance of three logics: In the short term, explosive demand for KV Cache in AI inference scenarios has triggered just-needed memory expansion. CXL memory controllers have entered a rapid scaling phase; In the medium term, CXL Switch is driving memory from "expansion" to "pooling," reconstructing data center resource scheduling patterns; In the long term, breakthroughs such as CXL over Optics will enable inter-cabinet and inter-rack memory interconnection, opening up tens of billions of dollars in market space. The core value of the CXL industry chain is concentrated in two tracks: CXL memory controllers and CXL Switch. The industry is currently in the initial phase of commercialization, with high technical barriers; leading enterprises with first-mover advantages will build strong moats.
The demand for computing power in AI model training and inference is growing exponentially, but the development of storage performance is lagging far behind CPUs. According to Synopsys research, over the past period, CPU performance improved much faster than storage, and the resulting mismatch severely limited processor computational capabilities.
Bottlenecks of traditional server architecture:
1) Memory bandwidth and capacity are strictly limited by the CPU’s native memory channel count
2) Taking Dell’s generations of servers as an example, the number of memory slots remains fixed at 32, relying solely on self-owned slots cannot meet the capacity needs in AI scenarios
3) GPUs can only directly access local video memory. To access system main memory, they must go through the CPU, resulting in significant data copying overhead
The CXL protocol is natively based on the PCIe physical layer architecture. Relying on three core protocols—CXL.io, CXL.mem, and CXL.cache—it not only breaks the memory capacity limitation of traditional CPU channels, but also turns PCIe slots into new storage access channels.
The three sub-protocols of CXL:
- CXL.io: Inherits underlying PCIe I/O functions, ensuring device connectivity;
- CXL.cache: Allows devices to cache data from the host memory and keeps caches consistent between devices and the host;
- CXL.mem: Supports direct sharing and unified addressing of memory resources.
The core value of CXL:
1) Capacity expansion: Using memory expanders to extend system memory capacity to more than 10 times that of local memory;
2) Memory pooling: Pooling the memory resources of CPU, accelerators, and storage devices to enable efficient cross-device collaboration;
3) Storage tiering: Offloading cold KV Cache data from HBM down to the CXL memory pool, greatly enhancing data interaction efficiency.
CXL generational upgrades feature the core characteristics of "speed improvement and protocol capability enhancement":
II. Why is It Important? Ongoing Technical Evolution
CXL’s direction of technology iteration is still under competition. Efficiency will be an important indicator determining the future prospects of technical solutions—
① Direction One: DRAM and NAND Flash hybrid expansion
Samsung’s CMM-H solution uses the CXL controller to centrally control DRAM and NAND Flash, intelligently sorting hot and cold data: frequently accessed hot data is stored in DRAM, while infrequently accessed cold data sinks to NAND Flash—balancing performance and cost.
② Direction Two: CXL over Optics
Optical interconnect technology offers unlimited bandwidth potential, ultra-low latency, high energy efficiency, and long-distance transmission advantages. Astera Labs released the industry’s first end-to-end PCIe over Optics demonstration in March 2026, achieving GPU cluster interconnections across racks and rows. H3C has also introduced its CXL Over Optical (CXL-O) optical interconnect solution.
③ Direction Three: Hybrid switch architecture
Marvell acquired XConn Technologies in January 2026 for $540 million, obtaining the world’s first hybrid switch chip supporting both CXL and PCIe. XConn’s Apollo 2 already supports PCIe 6.2/CXL 3.1 and is expected to ship in mid-2026.
According to Yole’s forecast:
- CXL-capable servers: Penetration rate reached 47% in 2024, expected to climb to 88% in 2026, stabilizing at 99% from 2028
- Servers actually using CXL functionality: Only 1% in 2026, expected to reach 13% in 2030
The core reason for the difference in penetration rate: Hardware compatibility is achieved naturally with CPU generational upgrades, while large-scale functional implementation requires overcoming multiple barriers including full-stack software adaptation, deployment costs, and commercial scenario validation.
CXL’s share in the global server DRAM market will continue to rise, expected to reach 15% by 2030:
1) CXL memory expansion: penetrates first, with low adaptation barriers
2) CXL memory pooling: speeds up with protocol iteration, share will surpass to 8.2% by 2030
Looking at future market size—
CXL controller market:
- Global sales in 2025: 1.482 billion RMB
- Projected in 2032: 11.79 billion RMB
- Compound annual growth rate (CAGR 2026-2032): 35.0%
CXL controller IP market:
- Market size in 2026: $564 million
- Projected in 2035: $1.719 billion
- Compound annual growth rate (CAGR 2026-2035): 44.99%
CXL Switch chip market:
- 2024: $1.8 million (initial commercialization)
- Projected in 2030: $730 million
- Compound annual growth rate (CAGR 2025-2030): 172%
III. What's Next? Two Core Links of the Industry Chain
The CXL industry chain is centered on two core sectors: CXL memory controllers and CXL Switch.
① CXL Memory Controllers: Foundation for Memory Expansion
CXL memory controllers are foundational for memory expansion, with high technical barriers. Major manufacturers include:
CXL Switch is the key hub for large-scale memory pooling architecture, enabling multi-host shared memory resources.
Market landscape:
- XConn: World's first CXL 2.0 Switch chip, XC50256, with 256 channels and total switching capacity of 2048GB/s
- Marvell: Acquired XConn for $540 million in January 2026, securing a lead in the CXL Switch track
- Broadcom: PCIe Switch market leader, about 35% market share, likely to expand into CXL Switch
- Microchip: PCIe Switch market share about 20%
③ Three-network architecture: Coordination of CXL, UALink, NVLink
Modern AI infrastructure needs three interconnect protocols to work together:
UALink 1.0 was released in April 2025, with per channel bandwidth of 200 Gb/s and support for up to 1024 accelerators interconnected. AMD, Intel, Google, Microsoft, among others, are all UALink Alliance members.
CXL technology is reaching a historic inflection point as it transitions from “technical exploration” to “large-scale commercialization.” The explosive demand of large AI models has created just-needed memory expansion, and CXL, through compute-storage decoupling and memory pooling, fundamentally reconstructs data center resource scheduling modes.
CXL is building the foundation for memory pooling in the AI era, and the historic opportunity to break the “memory wall” has begun.
Short term (1-2 years): Explosive demand for KV Cache in AI inference scenarios drives rapid scaling of CXL memory controllers; focus on manufacturers who have already served leading clients and have mass production capability;
Mid-term (2-3 years): The maturity of the CXL 3.0/3.1 protocol accelerates the rollout of memory pooling, and CXL Switch becomes a core growth engine; focus on technically leading switching chip manufacturers;
Long term (3-5 years): Breakthroughs in CXL over Optics enable inter-cabinet interconnection. Optical interconnect solutions open up tens of billions of dollars in market space.
The CXL protocol is not just a technological evolution, but a reshaping of Computer Architecture. In the era of trillion-parameter large models, whoever solves data flow efficiency between chips holds the ticket to the AI era.
Risk Warning and DisclaimerThe market involves risk; investment should be cautious. This article does not constitute individual investment advice, nor does it take into account the specific investment objectives, financial situation, or needs of any individual user. Users should consider whether any opinions, views, or conclusions in this article suit their particular situation. If you invest based on this article, responsibility is yours. ```