Jensen Huang visits Taiwan to "request production capacity"; TSMC urgently adds expansion plans and may raise capital expenditure for 2026.

“Without TSMC, there would be no Nvidia!” After Jensen Huang went to the doorstep to “order goods”, TSMC has reportedly been considering expanding its production capacity.

On November 14, according to Wind Chasing Trading Desk, Morgan Stanley's latest research report indicates that TSMC may be planning to add an extra 20,000 wafers/month of 3nm wafer capacity, beyond current expectations. The bank originally estimated TSMC's 3nm capacity for 2026 to be around 140,000-150,000 wafers/month, but new information suggests this number may be increased to 160,000-170,000 wafers/month.

This development closely follows Nvidia CEO Jensen Huang’s recent high-profile visit to the company. During his visit, Huang publicly stated that Nvidia’s business is “very strong” and has requested TSMC to provide more chip supply.

If the expansion plan is implemented, it will directly impact TSMC's capital expenditure. According to estimates, the newly added capacity will require about $5 billion to $7 billion in additional capital expenditure, potentially raising TSMC’s total capital expenditure for 2026 from the current expectation of about $43 billion up to the range of $48 billion to $50 billion. This potential increase in spending is seen by the market as a positive catalyst for the global semiconductor equipment industry.

This move not only reflects the continuing strong demand for AI, but also further confirms that the main bottleneck in the AI supply chain has shifted from back-end packaging to front-end manufacturing. The report clearly points out that CoWoS advanced packaging is no longer the biggest limiting factor—the real shortage lies in TSMC’s front-end wafer capacity and key materials like ABF substrates.

3nm Capacity Tightens, TSMC May Reallocate Old Production Lines

With Nvidia, AMD, Alchip and other clients rushing to place orders, TSMC’s 3nm capacity is becoming increasingly constrained. The report notes that the industry previously believed TSMC wanted to keep advanced process capacity fully utilized, so it was cautious about expansion. However, after requests from major AI clients like Nvidia, its 3nm capacity plans may have changed.

According to TSMC management at its earnings call, all newly constructed cleanroom space in Taiwan will be used for 2nm process expansion. This means that the 3nm expansion must take place within existing fabs. To resolve space issues, Morgan Stanley’s latest survey indicates that TSMC may consider moving 22/28nm equipment out of its Fab15 plant, keeping these machines for future European factories, thus freeing up valuable cleanroom space for new 3nm production lines.

According to the bank's forecast model, this adjustment will raise TSMC’s estimated 3nm total monthly capacity for 2026 from the previous 140,000-150,000 wafers to 160,000-170,000 wafers.

Capital Expenditures May Be Significantly Upgraded, Benefiting Equipment Makers

Behind capacity expansion is massive capital investment. Analyst Charlie Chan calculates in the report that, based on $300 million capital expenditure per thousand pieces of 3nm wafer capacity, an additional 20,000 wafers/month corresponds to $5 billion to $7 billion in investment, potentially bumping up TSMC’s 2026 total capital expenditures to $48-$50 billion.

This extra spending will significantly raise TSMC’s 2026 capital expenditure forecast. The report believes this potential capex increase will be positive for global semiconductor equipment sector sentiment. The bank therefore reiterates its “overweight” rating for TSMC, King Yuan Electronics, ASE and other industry companies.

Variations in TSMC's capital expenditures are a key indicator for the semiconductor industry's business cycle. Increasing capex generally means the company is strongly confident about future market demand, bringing direct benefits to upstream equipment suppliers.

CoWoS No Longer a Bottleneck, Front-End Wafer Is Key

For some time, the market has generally seen CoWoS advanced packaging as the main bottleneck for AI chip supply. However, the report highlights that this view may now be outdated.

Report analysis notes that despite major technology firms announcing huge datacenter power deployment plans, when converted into CoWoS demand, TSMC and other companies’ packaging capacity should be enough. The report says the true bottleneck lies in front-end wafer fabrication capability and in supply of ABF substrates and T-Glass (glass substrate) as other materials.

This assessment is also supported by the supply chain. According to Reuters, ASIC design service company Alchip has reiterated the dilemma of 3nm wafer shortages. This shows that even if back-end packaging capacity is sufficient, if front-end wafer supply falls short, AI chip final output will still be limited.

AI Demand Remains Strong, Nvidia and Other Clients Scramble for Capacity

The fundamental driving force behind TSMC’s consideration of urgent expansion comes from the insatiable “computing power hunger” of AI giants headed by Nvidia. During his Taiwan trip, Jensen Huang frankly stated “without TSMC, there would be no present-day Nvidia,” directly revealing how its growth relies deeply on TSMC’s capacity.

According to the report, among customers for TSMC’s 3nm process, Nvidia and another US client are the largest demand sources and are expected to dominate in 2025 and beyond. In addition, the report forecasts that by 2025, AI-related revenue will account for 25% of TSMC’s total revenue.

From Tesla’s 3nm AI5 chip design, to major cloud providers’ unceasing investment in AI servers, all signs point to one conclusion: for the foreseeable future, demand for cutting-edge process chips will remain robust. TSMC’s current expansion considerations are the most direct response to this market trend and also signal that the global semiconductor industry’s capital race will continue.

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The above fascinating content comes from Wind Chasing Trading Desk.

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