Ming-Chi Kuo: TSMC's CoPoS expected to begin mass production in the second half of 2028; Nvidia's latest AI chips may be the first to use it.

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The timeline for mass production and technical details of TSMC's next-generation advanced packaging technology, CoPoS, are becoming increasingly clear.

Renowned analyst Ming-Chi Kuo's latest research indicates that TSMC's CoPoS is expected to enter mass production in the second half of 2028, aiming to improve the mass production economics of ultra-large AI chip packaging. Its application scope targets packaging needs where the mask size exceeds 9.5 times. Kuo also specifically mentioned that Nvidia's latest generation AI chip, Feynman, may become one of the first adopters of CoPoS.

Mass Production Milestone Confirmed, Nvidia Feynman May Be the Launch Customer

According to Kuo's research, the mass production milestone for CoPoS is set for the second half of 2028, with the core driving force being the improvement of mass production economics for ultra-large AI chip packaging. Currently, the packaging size of AI computing chips continues to expand, and ultra-large packaging solutions that break the single mask limitation pose higher requirements for yield and cost control, which CoPoS is designed to address.

On the potential customer side, Kuo pointed out that Nvidia's Feynman chip could be among the first users of CoPoS. Feynman is Nvidia's planned next-generation AI chip; if the timing aligns, it will coincide with CoPoS’s mass production window in the second half of 2028.

Glass Substrate Structure Analysis: Three-Layer Architecture, Coexisting with ABF

Kuo describes in detail the structure of the glass core substrate in CoPoS. This substrate uses glass as the core layer, with ABF buildup layers (ABF-GCP) covering both the top and bottom, forming a three-layer structure. The glass processing involves key processes such as TGV (Through Glass Via), copper filling, and metallization, which are technically demanding.

In terms of material specifications, CoPoS uses glass in two places: one is a temporary glass carrier plate sized 310×310mm; the other is a 250×250mm glass panel for testing, and a 510×515mm glass panel for mass production, with the latter being processed and cut into glass core substrates.

Clarifying Three Misconceptions: Glass Is Not an Interposer, Does Not Replace ABF

Kuo specifically addresses three technical misconceptions circulating in the industry.

Misconception 1: CoPoS uses a glass interposer. Kuo points out that the glass in CoPoS is not an interposer; the interconnection function is realized by the RDL (redistribution layer) on the chip side and TGV plus ABF buildup layers on the glass core substrate side. These jointly complete the interconnection, rather than being solely handled by a glass interposer.

Misconception 2: Glass replaces ABF. Kuo clearly states that glass and ABF coexist in the CoPoS substrate stack, not as replacements, and the above-mentioned three-layer structure confirms this.

Misconception 3: Chips are placed directly on the glass. Kuo clarifies that the chip is actually attached to the ABF buildup layer surface of the glass core substrate, not in direct contact with the glass.

Kuo believes that CoPoS will continue to strengthen TSMC's competitive advantage in the field of advanced packaging, which is expected to last until around 2032, supporting TSMC’s long-term position in the AI chip packaging market.

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