Morgan Stanley: Answering Five Key Questions About the Asian AI Semiconductor Supply Chain

Morgan Stanley's latest research report cuts through the noise of AI infrastructure investments, based on on-site research of the Asian supply chain, addressing the five core questions the market cares most about: Nvidia Rubin Ultra packaging solution, LPU foundry selection, Samsung HBM base die shifting to TSMC, Broadcom’s cooperation with Google and its impact on MediaTek, and the practical significance of new computing power deployment on chip demand.

In the field of advanced packaging, Morgan Stanley states that TSMC’s monopoly position in CoWoS/SoIC is continuously strengthening, with production capacity expanding to 160,000-170,000 wafers per month by 2027, enough to meet surging computing power demand. However, technical challenges such as interposer substrate warpage for ultra-large chips still need to be addressed.

For custom chips, MediaTek’s development of Google’s 3nm TPU (ZebraFish) is progressing smoothly, with mass production expected in the second half of 2026. The report maintains revenue forecasts of $1.6 billion in 2026 and $10 billion in 2027, believing this will be a decisive factor for MediaTek's valuation re-rating.

Regarding the foundry landscape, Nvidia is gradually introducing Samsung as a complement to TSMC, and the LP35 node in 2027 may adopt a dual-supplier strategy, breaking expectations of TSMC’s monopoly on Nvidia's advanced process nodes.

Nvidia Rubin Ultra: Package two or four dies per chip? What's the impact?

The market is highly focused on whether Nvidia's 2027 Rubin Ultra will package two or four compute dies in a single package. This essentially depends on whether TSMC’s CoWoS-L technology can support chip designs as large as nine reticle sizes in a cost-effective manner—such a solution would contain four compute dies, two I/O dies, and eight to ten HBMs.

Regardless of whether Rubin Ultra ultimately adopts a two- or four-die configuration, it will not materially change Nvidia’s consumption of TSMC wafer capacity. TSMC’s CoWoS roadmap shows that nine reticle sizes can be supported by 2027; it's technically feasible, but reliability issues such as interposer warpage remain to be solved. If these bottlenecks can’t be overcome, Intel’s EMIB-T could seize TSMC’s market share in projects like Google’s 2nm TPU.

Nvidia LPU demand explosion: Who benefits, Samsung or TSMC?

Nvidia’s Groq 3 LPU is scheduled for launch in the second half of 2026, featuring liquid-cooled LPX racks, each cabinet containing 256 LPUs, each with 128GB on-chip SRAM and 640 TBps extended bandwidth, focused on low-latency AI inference scenarios. The current LP30 version uses Samsung’s 7nm process.

Supply chain surveys show that starting from LP35 (4nm)—which will be mass-produced alongside Rubin Ultra in 2027—Nvidia may adopt a dual-supplier procurement strategy between TSMC and Samsung. LP40 (expected 3nm) is planned for 2028, paired with the Feynman platform, adopting discrete SRAM and TSMC SoIC 3D stacking.

For SoIC capacity, TSMC expects to reach 14,000 wafers per month in 2026, expand to 28,000 wafers per month in 2027, and further expand to 45,000 wafers per month in 2028.

Will Korean HBM base dies shift to TSMC 3nm?

Because HBM4e and HBM5 base dies require extensive customization and IP support, TSMC’s 3nm process will become a key global node for HBM base dies by 2028.

Latest supply chain information indicates that TSMC will further convert 10,000-20,000 4/5nm wafer capacity to 3nm in Fab 18 Phase 3, preparing for customized HBM4e and HBM5 base die demand, including that from Korean HBM suppliers.

In terms of investment implications, AI memory (including SRAM and HBM base dies) will become a major growth driver for TSMC starting in 2028.

What is the impact of the Broadcom-Google announcement on MediaTek's TPU opportunities?

The Broadcom-Google partnership announcement once sparked doubts about MediaTek’s strategic position in the TPU supply chain. But the report clearly states that this event does not change the positive outlook for MediaTek’s 3nm TPU (ZebraFish).

Supply chain checks confirm ZebraFish will be mass-produced as scheduled in the second half of 2026. The shipment assumption of 400,000 units in 2026 (corresponding to about $1.6 billion in revenue) "should be solidly attainable." The current 3nm TPU is undergoing ECO modifications on several metal layers due to slightly higher-than-expected power consumption, but this does not affect the mass production schedule. Google is conducting simultaneous testing and verification. The mass production stage will adopt a new mask set incorporating the design changes, with more stable chip performance and quality.

More importantly, the report is optimistic about MediaTek’s ABF substrate supply in 2027, reaffirming the highest market forecast: 2.5 million units shipped in 2027, contributing about $10 billion in revenue, and maintaining an “overweight” rating.

Looking at the full Google TPU shipment forecast, total volume will grow from 2.4 million units in 2024 to 6 million units in 2027 and 7 million units in 2028. MediaTek's ZebraFish (v8, 3nm) and HumuFish (v10, 2nm) will each contribute significant shares in 2026 and 2027, respectively.

How much chip demand does new compute deployment imply?

Recently, the market has announced a lot of new compute deployment plans, including the 2GW AWS-OpenAI project and Google-Broadcom’s 3.5GW project. Translating these large power numbers into actual wafer demand, the core conclusion is: electricity is not the bottleneck for TSMC chip demand—ABF substrate and HBM supply are the real constraints.

According to estimates, over the lifetime of these projects, the implied total consumption of TSMC CoWoS wafers is about 953,000 pieces, while the front-end 2nm and 3nm wafer consumption is about 652,000 pieces. Assuming OpenAI-related contracts are executed within three years, it is estimated that these projects will drive annual CoWoS demand at TSMC to 259,000 wafers in 2027.

Morgan Stanley believes this target is fully achievable, as TSMC plans to expand CoWoS capacity to 160,000-170,000 wafers per month (160-170kwpm) by the end of 2027, enough to cover the incremental demand mentioned above.

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