Nomura's major report: From silicon to glass, from GPUs to optical communication, AI is reshaping the entire semiconductor industry chain!

The demand for AI computing power is changing the growth model of the semiconductor industry. Over the past decades, improvements in chip performance mainly relied on Moore's Law: making transistors smaller and increasing density. However, as advanced processes continue shrinking, metal spacing, power consumption, leakage, heat dissipation, yield, and cost are all approaching their limits. Simply betting on “smaller nodes” is no longer enough.

According to Chase Wind Trading Desk, the team led by Donnie Teng, Nomura Securities Asia Pacific Technology Analyst, pointed out in a research report that the growth logic of the semiconductor industry has shifted from increasing transistor density to “combination innovation of 3D transistors, backside power delivery, and diverse new materials.” This statement is the core of the entire research: AI is not just pulling up GPU demand, but is forcing a rewrite of fundamental manufacturing processes for chips.

The more direct investment implication is that materials, consumables, substrates, specialty gases, and compound semiconductors—previously viewed as supporting segments—are becoming crucial variables determining advanced chip performance. Especially starting from 2027, technologies such as backside power delivery, wafer bonding NAND, glass core substrates, and photonic SOI will enter a volume growth phase, possibly ushering in a systemic revaluation of the materials sector.

TSMC remains the most important amplifier in this chain. Expansion of advanced capacity, SoIC hybrid bonding, introduction of high NA EUV, and increases in localized procurement ratios will all transmit orders to equipment, materials, and component companies. Unlike the last semiconductor cycle, this round is not a single process upgrade, but a simultaneous switch across structure, packaging, and materials.

Moore's Law Has Not Failed, But “Just Shrinking” Is No Longer Enough

The problem with advanced process technology is not that progress can't continue, but that the costs are increasingly high.

From 7nm to 3nm, and then to the next node, further compression of metal spacing brings severe power, leakage, and heat dissipation challenges. The patterning capability of low NA EUV and DUV is also limited; multiple exposures can solve some precision issues, but cost and yield pressures increase accordingly.

Therefore, advanced logic chips are turning to more complex structural innovations. GAA (gate-all-around) transistors will continue evolving toward stacked cFETs, with the primary goal of enhancing gate control of the channel and increasing integration density.

Backside power delivery is more like a “rewiring.” The power network is moved from the front to the back of the wafer, separated from the signal network, and supplied through wider, lower-resistance metal lines, reducing IR voltage drop and backend wiring congestion. This leaves room for further shrinking standard cells.

These changes are not just conceptual; they directly impact process consumption. CMP steps for advanced process chips increase from 45–55 steps in traditional processes to 55–70 steps, a rise of about 20%–30%. Backside power also requires stacking two wafers, nearly doubling wafer consumption, boosting demand for wafer thinning, grinding, and bonding.

Timing is critical: related equipment and materials demand starts ramping in 2026, enters rapid volume growth in 2027, and is expected to become standard for advanced chips by 2030.

High NA EUV Truly Drives Photolithography Materials Upgrade

High NA EUV is the core equipment for the next generation of advanced processes. The numerical aperture rises from 0.33 to 0.55, resolution improves to 8nm, aiming to eliminate the need for multiple exposures below the 3nm node. It will reach mass production as early as 2029. Each machine costs over $400 million.

But high NA EUV is not just about buying equipment. The higher numerical aperture means photons hit the wafer at shallower angles, requiring thinner photoresist layers, otherwise shadow effects occur. Conventional chemically amplified photoresists under ultrathin conditions lack sufficient etch resistance, photon absorption, and pattern precision.

Metal oxide photoresists thus become key materials. These photoresists use metal oxides and offer stronger etch selectivity, higher resolution, and better roughness control, making them more suitable for high NA processes.

The value change is clear: existing EUV photoresist is about $5,000 per gallon. High NA EUV-specific metal oxide photoresist ranges from $10,000–$40,000 per gallon, a 2–8 fold price increase.

The upgrade for photolithographic materials isn’t limited to photoresist. Mask materials also need to be replaced; traditional tantalum-based absorption layers can't meet the reflection angle requirements of high NA processes. Ruthenium and molybdenum-based materials are emerging as alternatives. Developer, cleaning solution, anti-reflective bottom coating, edge stripping solution, and other supporting materials must also be upgraded.

The Next Battle in Advanced Packaging May Be Glass Substrates

AI chips increasingly rely on advanced packaging, because chips that keep growing in size and computing power encounter multiple limits in power, interconnection, heat dissipation, and manufacturing yield.

SoIC hybrid bonding will see a surge in demand in 2026–2027, mainly for high-density integration of AI chips and HBM. Compared to traditional micro-bump processes, hybrid bonding achieves direct Cu–Cu connections, boosting interconnect density by an order of magnitude and bandwidth from 200GB/s to 1TB/s.

The process requirements are high: wafer surface flatness must be controlled at the nanometer level, making CMP a key step; bonding equipment needs precision below 0.2 microns; cleaning, surface activation, and alignment must all be upgraded. Besi, as a leader in chip-level and wafer-level hybrid bonding equipment, will see order recovery from 2026 driven by AI chips, optical communication, and HBM demand.

Packaging substrates are also changing materials. Compared to traditional ABF organic substrates, glass core substrates offer lower thermal expansion, higher flatness, better heat dissipation, and lower signal loss—ideal for large, high-power, high-speed chips.

In the base-case scenario, Broadcom is expected to be the first to apply glass core substrates to switch ASICs in 2027, and Intel is advancing it as a core material for next-generation packaging. However, glass substrates are not fully mature; mass production is still constrained by high costs, RDL dielectric layer delamination and stratification, and yield ramp issues.

The true process challenge is TGV (Through-Glass Via) perforation. Laser drilling, etching, metal filling, and planarization determine final performance. Ingentec and other companies with TGV patent technologies are entering this supply chain.

Optical Communication Brings Compound Semiconductors to the Forefront

Bottlenecks in AI data centers are not only in GPUs, but also in communications. High-speed optical modules and co-packaged optics (CPO) are driving the optical communication industry upward, with 1.6T module adoption and silicon photonics conversion as two main trends.

Indium phosphide substrates are used for EML and CW laser chips, the core materials for optical modules. Due to indium export controls and production yield bottlenecks, indium phosphide will see continuous supply shortages and high prices from 2025–2027.

The other direction is photonic SOI wafers for silicon photonics integrated chips (PIC). Cost is only 25% that of indium phosphide substrates, more suitable for mass production, and is the core material for CPO solutions. Soitec holds a 70% global market share of photonic SOI wafers, with GlobalWafers and Silicon Industry Group following suit.

By 2027, demand for photonic SOI will ramp rapidly, becoming the main growth driver for SOI wafer business.

12-Inch Silicon Wafer Supply and Demand Tightens Starting 2027

As AI-driven changes in manufacturing processes happen, demand for silicon wafers will rise again.

Market demand typically grows about 5% per year. TSMC, Samsung, and Intel’s capacity expansions add another 2–3 percentage points annually. Backside power delivery, wafer bonding NAND, and photonic SOI—three new technologies—will contribute an additional 2–3 percentage points per year.

In total, annual demand for 12-inch silicon wafers is set to grow nearly 10%.

Supply won't catch up as fast. Silicon wafer capacity expansion is limited by equipment lead times and capex pace and cannot immediately meet demand. Starting in 2027, supply gaps will appear; GlobalWafers, Shin-Etsu, SUMCO and other leaders will regain bargaining power, and long-term contract prices will rise. Ancillary businesses such as wafer recycling and test wafers will also benefit.

TSMC Capacity Expansion and Local Procurement are Catalysts for Supply Chain Growth

TSMC’s capex in 2027 is expected to hit $70 billion, with 26 global advanced wafer and packaging plants ramping up—18 of which are in Taiwan, while U.S., Japan, and Germany plants ramp in parallel.

Advanced capacity releases will directly drive demand for equipment, materials, and components. More importantly, TSMC is steadily increasing the ratio of local and regional procurement for equipment, components, and materials, covering raw materials, components, consumables, and site equipment.

This opens a window for regional suppliers to enter the supply chain. Photolithography ancillaries, CMP consumables, specialty gases, silicon wafers, and packaging materials are the focus of local procurement. Taiwan and Mainland China materials companies, if certified, could see market share gains far faster than usual cycles.

Clear Industry Roll-Out Rhythm: 2027 Becomes the Turning Point for the Whole Supply Chain

The rhythm of this industry chain can be condensed into a few key dates:

2026: GAA transistors, SoIC hybrid bonding, InP substrates start, small-volume deliveries emerge.

2027: Backside power delivery, wafer bonding NAND, glass core substrates ramp in volume, enter larger scale production.

2028: DRAM-on-logic architecture enters mass application; edge AI and automotive electronics become key drivers.

2029–2030: High NA EUV mass production; metal oxide photoresists and new mask materials are fully adopted.

The materials sector has underperformed equipment in the past decade. One reason is that high-priced AI chips more easily boost system and equipment revenues; another is that Moore's Law mainly favored equipment, while material demand fluctuated more during industry downturns. Now change has arrived: 3D structures, new materials, advanced packaging are all advancing, and material consumption and value are rising.

The most important aspect of this change is: AI hasn't just brought one round of GPU boom; it has pushed semiconductor manufacturing from “process shrinkage” to “structural innovation + material replacement + advanced packaging.” From silicon wafers to glass substrates, from GPUs to optical communication, the value distribution of the supply chain is being rewritten.

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