Report: SK Hynix is exploring new HBM4 packaging technologies, aiming at Nvidia's top performance targets.

SK Hynix is developing an innovative packaging technology for next-generation high-bandwidth memory, aiming to break through HBM4 performance bottlenecks without significantly increasing capital expenditures.

According to TrendForce citing ZDNet on Tuesday, industry sources revealed that SK Hynix is advancing an improved packaging architecture scheme, with core measures including increasing DRAM chip thickness and reducing DRAM layer spacing. The technology is currently in the validation stage. If successfully commercialized, the scheme is expected to help SK Hynix meet Nvidia's top performance targets for sixth-generation HBM4, and provide a foundation for subsequent product performance improvements.

For the market, the potential significance of this technology lies in its low capital investment attribute—if mass production is achieved, SK Hynix is expected to further consolidate its technological leadership in the HBM competitive landscape, while providing more competitive memory solutions for Nvidia and other downstream customers. However, the report also points out that scaling the technology to the stage of mass production may still face challenges.

Thickening DRAM to enhance stability, reducing layer spacing to boost efficiency and transmission speed

The core constraint to HBM4 performance improvements stems from its I/O count doubling to 2048 compared to the previous generation. According to reports, denser I/O layouts significantly increase bandwidth while also greatly increasing the risk of signal interference. At the same time, efficiently transmitting voltage from the bottom logic chip to the top DRAM constitutes a technical challenge for power delivery.

These two challenges both point toward the need for optimized packaging architecture, which is exactly the starting point for SK Hynix’s technical exploration.

The first core measure of SK Hynix’s new plan is to moderately increase the thickness of the upper DRAM chips. Traditional processes usually thin DRAM through back grinding to meet the 775-micron overall height requirement for HBM4. However, excessive thinning can lead to performance decline and makes the chip more sensitive to external impacts.

By increasing DRAM thickness, SK Hynix aims to enhance the structural stability of HBM4, thus reducing the risk of yield loss caused by physical stress.

The second measure is to reduce DRAM layer spacing. Without increasing the overall packaging height, tighter layer arrangements help accelerate data transfer speeds and reduce the power consumption needed to supply voltage to the top DRAM.

However, narrowing layer spacing brings new technical challenges: the stability of MUF (Molded Underfill) injection will be significantly reduced. As a protective and insulating material, uneven filling or voids in MUF will directly cause chip defects.

To address this, SK Hynix has developed a new packaging technology whose core idea is to narrow DRAM layer spacing while maintaining stable yields, without making large-scale changes to existing processes or equipment. According to reports, recent internal tests have yielded positive results.

Commercialization prospects expected, mass production challenges remain

If the technology is successfully commercialized, its most significant advantage is improving HBM performance without large-scale capital expenditure, which is important for semiconductor manufacturers seeking a cost-effectiveness balance amidst intense R&D competition.

However, the report also notes that moving from the validation stage to large-scale mass production still faces unresolved challenges in technical stability and process consistency. Currently, SK Hynix is actively promoting relevant validation work, but the commercialization timetable remains unclear.

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