Samsung Electronics showcases HBM5 for the first time, betting on next-generation AI memory competition.

```

Samsung Electronics unveiled the eighth-generation high-bandwidth memory HBM5 prototype for the first time at Computex 2026, marking the Korean chip giant’s accelerating product deployment in the AI memory market. Amid comprehensive increases in memory prices, market expectations for Korean memory manufacturers’ profits this year have been significantly raised.

Samsung Electronics CTO Song Jae-hyuk stated at the exhibition that as AI systems become increasingly complex, competitiveness across the entire value chain—from memory and wafer foundry, to logic chips and packaging—becomes ever more crucial. The core technical highlight of HBM5 is a thermal management innovation named Heat Path Block (HPB), which guides heat flow between semiconductor wafers, effectively alleviating heat accumulation in high-density stacked chips, thereby enhancing performance stability and operational reliability.

At the HBM4E level, Samsung delivered 12-layer HBM4E samples to major global customers in late May, becoming the first manufacturer in the industry to ship this product. HBM4E offers a stable pin transmission speed of 14Gbps, expandable to 16Gbps—over a 20% improvement over HBM4; each stack’s bandwidth reaches 3.6TB/s, with a capacity of 48GB, more than a 30% increase over the previous generation.

Sharp increases in general DRAM prices have significantly strengthened the pricing dominance of Samsung and SK Hynix in HBM, leading to a sharp upward revision of both companies’ profit expectations. Morgan Stanley forecasts Samsung’s annual operating profit may increase by 464% year-on-year, and SK Hynix’s by approximately 280%.

HBM5: Breakthrough in Thermal Management and Advanced Process Roadmap

The HBM5 prototype shown by Samsung centers on the HPB thermal management technology as its core innovation. As AI model computation demands continue rising, storage bandwidth increases, intensifying heat buildup issues in densely stacked chips, which directly threaten chip performance and lifespan. Samsung states that HPB guides heat between semiconductor wafers, helping to dissipate it from critical areas, thereby improving overall operational stability.

This technology has already been validated on the HBM4E platform and is planned for official commercial use with HBM5. Song Jae-hyuk said the pace of advancement will depend on customer demand, with the possibility of an early commercial launch not excluded. In terms of process, HBM5 plans to incorporate Samsung’s sixth-generation 10nm-class DRAM process (1c DRAM) and 2nm logic node.

Song Jae-hyuk further noted that implementing HPB requires redesigning and integrating multiple layers of the chip architecture. As a comprehensive semiconductor manufacturer covering memory, wafer foundry, and packaging, Samsung possesses synergistic advantages across these links that competitors find hard to replicate. Besides, Samsung is preparing to become the industry's first to deploy hybrid copper bonding advanced packaging technology, which can further improve thermal dissipation and chip performance; samples have already been provided to multiple customers.

HBM4E: Dual Upgrade in Speed and Capacity, Mass Production Imminent

Outside the vision for HBM5, Samsung also showcased wafers and chipsets of the HBM4E platform at Computex. Exhibition information shows this product delivers pin transmission speeds up to 14Gbps, maximum bandwidth up to 4TB/s; the core chip uses the 1c DRAM process, and the logic base chip is made by Samsung’s foundry using a 4nm process.

Samsung’s May 29 announcement revealed the delivered 12-layer HBM4E samples improved energy efficiency by 16% over the previous generation, and thermal resistance by more than 14%, helping extend reliability and lower energy consumption in high-load data center scenarios. HBM4E shares core technology paths with HBM4, aiming to enhance process stability and yield. Sang Joon Hwang, Executive VP of Samsung’s Memory Development, stated HBM4E again highlights Samsung’s differentiated technological advantage, and the company will continue driving growth in the global AI memory market.

In product line planning, aside from the existing 12-layer 48GB version, Samsung will launch 32GB (8-layer) and 64GB (16-layer) versions to meet varying customer needs, and the mass production schedule will align with customer timelines.

Comprehensive Rise in Memory Prices, Korean Manufacturers Expected to Achieve All-Time Profit

While Samsung actively deploys AI memory technology, the overall memory market price trend also provides strong support. The market believes that after a sharp rise in general DRAM prices, margins are now close to HBM levels, so both Samsung and SK Hynix do not need to rely on HBM volume boosts to maintain revenue, enabling a tough bargaining position on pricing.

Samsung has taken a prudent capacity allocation strategy, not excessively shifting DRAM capacity to HBM, which further supports high HBM price ranges. According to reports, negotiated prices of Samsung HBM4 have reached about $700, 20%–30% higher than the previous generation HBM3E.

With HBM, general DRAM, and NAND flash prices rising together, Korean memory manufacturers are expected to see comprehensive improvements in profitability. Morgan Stanley forecasts Samsung Electronics’ annual operating profit this year to reach about 24.57 trillion won, a 464% increase year-on-year; SK Hynix’s is expected to be about 17.94 trillion won, an increase of around 280%. These two companies’ performance improvement is expected throughout the year.

Risk Warning and DisclaimerThe market carries risk and investment must be cautious. This article does not constitute individual investment advice and does not take into account the special investment objectives, financial conditions, or needs of any individual user. Users should consider whether any opinions, viewpoints, or conclusions in this article suit their specific situation. Investments made on this basis are at your own risk. ```