Samsung HBM roadmap: HBM4 to dominate shipments this year, HBM5 substrates upgraded to 2 nanometers

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Samsung Electronics is accelerating its next-generation high-bandwidth memory deployment. While HBM4 officially enters mass production this year, Samsung is already looking ahead to the next generation product—planning to upgrade the base die process for HBM5 from 4nm to 2nm and use 1d DRAM as the core stacked memory for HBM5E. Meanwhile, HBM4 will account for over half of Samsung’s total HBM shipments this year, with overall HBM capacity increasing more than threefold compared to last year.

According to ETNews and Yonhap News Agency, Samsung’s Head of Memory Development and Vice President Hwang Sang-jun revealed this plan at Nvidia’s GTC conference. He stated that the base die for HBM5 will use Samsung’s 2nm foundry process, marking a generational upgrade from the 4nm process used for HBM4 and HBM4E, to meet the higher memory performance demand of next-generation AI workloads.

Regarding capacity targets, Hwang Sang-jun said that Samsung aims for HBM4 to account for more than 50% of all HBM shipments this year, while total HBM production will increase more than three times compared to last year. This shows Samsung’s determination to expand in the AI storage market and has a direct impact on the supply landscape of high-end DRAM and downstream AI accelerator supply chains.

Beyond the storage roadmap, Hwang Sang-jun also revealed that the Groq 3 inference chip is being manufactured at Samsung’s Pyeongtaek campus, with mass production targeted for late Q3 to early Q4 this year, and order volumes have already exceeded expectations. Thus, Samsung is further extending from being a pure memory supplier to a full-stack AI accelerator partner.

HBM5 Base Die Process: Leap from 4nm to 2nm

According to ETNews, Hwang Sang-jun stated clearly at Nvidia GTC that HBM5’s base die will adopt Samsung’s 2nm foundry process, which is a major upgrade over the 4nm process used for HBM4 and HBM4E. Upgrading the base die process usually helps improve memory bandwidth and power efficiency.

Hwang Sang-jun pointed out that while using cutting-edge processes increases costs, introducing advanced technology is inevitable to achieve the target performance for HBM. This statement clarifies Samsung’s technical path of performance leaps driven by process upgrades in high-end AI storage.

For HBM5E, ETNews reported that Hwang Sang-jun said the product will use 1d DRAM as the core stacked memory, marking another upgrade compared to the 1c DRAM used for HBM4 and HBM4E.

The 1d DRAM used for HBM5E is still in internal development at Samsung and has not yet been commercialized. However, according to ETNews citing informed sources, Samsung has achieved strong performance and good test yields on the technology, indicating positive signals toward mass production.

HBM4 Leads Shipments This Year, Capacity Up Over Threefold Compared to Last Year

According to Yonhap News Agency, Hwang Sang-jun stated that Samsung’s goal this year is for HBM4 to account for more than 50% of all HBM shipments, with annual HBM production increasing more than threefold compared to last year.

HBM4 is officially entering mass production this year. Samsung plans to both scale up mass production and significantly expand overall HBM capacity to match the rapidly rising demand for high-bandwidth memory in the AI chip market. If these capacity expansion plans are realized, it will have a substantial impact on the supply structure of the high-end DRAM market.

Groq 3 Foundry: Samsung Expands Its Role in NVIDIA’s Ecosystem

Outside the storage business, Samsung is further expanding its position in the AI accelerator supply chain by manufacturing the Groq 3 inference chip.

According to Yonhap News Agency, Hwang Sang-jun said NVIDIA CEO Jensen Huang has publicly acknowledged Samsung’s contribution for Groq 3, which is being produced at Samsung’s Pyeongtaek campus, with mass production targeted for late Q3 to early Q4 this year, and current order volumes have exceeded expectations.

According to Yonhap News Agency, the Groq 3 chip die area exceeds 700 square millimeters, with each wafer only yielding around 64 chips, far fewer than the typical 400 to 600. Around 70% to 80% of the chip area consists of SRAM, enabling rapid inference computation on-chip without relying on external HBM. Hwang Sang-jun also revealed that Groq was already a Samsung foundry client before signing a licensing agreement with NVIDIA.

According to SEDaily, Samsung’s foundry for the Groq 3 LPU chip is widely seen as a major sign of becoming a core full-stack platform partner for next-generation AI accelerators. After Samsung’s foundry department entered NVIDIA’s supply chain, Samsung’s role has expanded from memory supply to LPU manufacturing, deepening collaboration within the NVIDIA ecosystem.

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