Samsung HBM4E yield surpasses 70%, seventh-generation AI memory development enters stable phase

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Samsung Electronics has achieved a series of milestones in the roadmap for AI memory technology. Following its lead in mass-producing sixth-generation high-bandwidth memory HBM4, Samsung has also made positive progress in the development of seventh-generation HBM4E and next-generation DRAM processes, laying a solid foundation for consolidating its technological leadership in the next round of AI memory competition.

According to semiconductor industry sources, Samsung Electronics CTO and head of the Semiconductor Research Institute, Song Jai Hyuk, stated at an internal business briefing for the DS (Device Solutions) division on June 30 that the yield rate for HBM4E reliability testing has risen to over 70%. The industry typically considers a yield rate above 80% as the threshold for process stability or "mature yield," and although HBM4E is still in the reliability testing phase, a level of over 70% is regarded as a sign that development has officially entered a stable zone.

At the same time, Song Jai Hyuk revealed at the same event that the next-generation 10nm class seventh-generation DRAM process (D1d) has achieved a technological advantage over competitors, with plans to complete Production Readiness Approval (PRA) by this November. The combination of these two achievements has made the market more optimistic about Samsung’s competitive outlook in the next-generation AI memory arena.

HBM4E Development Accelerates, Sample Evaluations Progressing Smoothly

In February this year, Samsung was the first to achieve mass production and shipment of HBM4. On May 29, Samsung further disclosed detailed technical specifications of the 12-layer HBM4E product and sent samples to major clients.

HBM4 will be used in NVIDIA’s AI accelerator “Vera Rubin” which will be launched later this year. HBM4E, as its successor, is planned for NVIDIA’s next-generation AI accelerator “Vera Rubin Ultra” to be released next year. According to industry insiders, as sample evaluations by major clients proceed steadily, mass production development for HBM4E is also progressing smoothly.

In this context, the increase of the reliability test yield rate to above 70% is significant. Though this figure has yet to reach the generally recognized mature yield standard, given the current stage of product development, it is widely interpreted as a positive signal that HBM4E is rapidly converging toward mass production conditions.

D1d Process Advancing, Targeting Mass Production Certification in November

Regarding next-generation DRAM process development, Song Jai Hyuk stated that the D1d process has achieved a technological lead over its competitors and aims to obtain Production Readiness Approval (PRA) by November this year.

PRA is the final internal quality assessment procedure before product shipments, providing comprehensive validation of yield, performance, and production efficiency to determine if mass production conditions are met. Once passed, formal mass production can commence.

The strategic significance of the D1d process goes beyond DRAM itself. Samsung plans to fully introduce this process starting with the eighth-generation HBM5. The industry believes that if D1d development proceeds as scheduled, it will create positive chain effects on the overall competitiveness of next-generation DRAM and follow-up HBM5 products.

Contradictions in R&D Personnel Compensation Emerge

While reporting these technological advancements, another issue has surfaced within Samsung’s DS division. It is reported that after this briefing, internal dissatisfaction within the R&D organization regarding the recognition of roles and compensation structures has intensified, with some members calling for greater recognition of the R&D organization’s contributions.

Previously, labor and management at Samsung’s DS division agreed to set up a “Special Operational Performance Bonus” system, funded by 10.5% of operating profits. However, within the DS division, there remain large gaps in performance bonuses between the memory business, the public sector including research institutes, and non-memory businesses (such as System LSI and foundry). Calls for improving the compensation structure are increasing.

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