Samsung unveils next-generation storage roadmap: HBM5 offers twice the performance of HBM4E, and zHBM delivers eight times the acceleration performance.

Samsung unveils next-generation storage roadmap: HBM5 offers twice the performance of HBM4E, and zHBM delivers eight times the acceleration performance.

At SEMICON Taiwan 2026, Samsung Electronics unveiled a detailed technology roadmap for its next-generation high-bandwidth memory (HBM) and next-generation storage architecture, covering several cutting-edge technologies such as HBM5, zHBM, and zNAND-O, demonstrating the South Korean storage giant's long-term strategic intentions in the AI infrastructure storage market.

At an event on September 1st, Jangseok Choi, Corporate Vice President of Memory Product Planning at Samsung, stated that the goal of HBM5 is to achieve twice the performance of HBM4E, a 20% increase in performance per watt, and a 20% reduction in thermal resistance. Samsung had previously revealed some related progress at Hot Chips 2026 in August.

Samsung also announced that it is developing a new architecture, zHBM, with a target performance of 8 times that of HBM4E, a 3x increase in performance per watt, and a 75% to 90% reduction in thermal resistance.

This series of technological upgrades directly addresses the dual demands for high bandwidth and heat dissipation brought about by the rapid expansion of AI accelerator computing power, and has important reference significance for AI chip supply chain and related infrastructure investment.

HBM5: Process upgraded to 2nm, mass production expected in 2028

Reports indicate that HBM5 aims for twice the performance of HBM4E, with significant improvements in power efficiency and thermal management. Samsung has upgraded the manufacturing process of its HBM5 base die from the 4nm process used in HBM4 and HBM4E to its own 2nm node, marking a significant step forward for HBM in terms of process technology.

Regarding the number of stacking layers, Samsung is preparing three DRAM stacking solutions for HBM5: 12-layer, 16-layer, and 20-layer, to meet the capacity and performance requirements of different application scenarios. Mass production is expected to begin after HBM4E, around 2028.

The 20% reduction in thermal resistance is particularly crucial – as the power consumption of AI accelerators continues to rise, the heat dissipation capacity of HBM is increasingly becoming a system bottleneck, and this improvement helps maintain the stable operation of high-performance computing systems.

zHBM: A disruptive architecture where storage is directly stacked on top of the processor.

Samsung positions zHBM as a completely new architecture, distinct from traditional HBM. Traditional HBM places memory next to the AI accelerator (xPU), while zHBM stacks memory directly on top of the processor, achieving higher bandwidth and better power consumption by significantly shortening the data transfer path.

Samsung's goal is for zHBM to achieve eight times the performance of HBM4E, three times the performance per watt, and a 75% to 90% reduction in thermal resistance. If this performance leap is achieved, it will represent a fundamental breakthrough in bandwidth density and energy efficiency for existing HBM architectures.

zHBM is expected to launch after 2029 and is part of Samsung's longer-term technology reserve strategy.

zNAND-O: Achieving near-DRAM speeds with NAND density

In the NAND storage field, Samsung has also introduced forward-looking technology directions. The zNAND-O project will begin sampling in 2028, aiming to achieve 10 times the storage density of DRAM, while achieving 7 times the read bandwidth and power efficiency of NAND.

The technology was designed to meet the dual demands of generative AI and large language models (LLM) for "DRAM-level speed and NAND-level capacity"—as the model size continues to expand, the trade-off between speed and capacity in existing storage architectures is increasingly becoming one of the bottlenecks restricting the efficiency of AI inference and training.

CUBE Strategy: A Four-Dimensional Approach Including Capacity, Utilization, Bandwidth, and Efficiency

At the Memory Executive Summit held concurrently with SEMICON Taiwan 2026, Samsung also systematically elaborated on its "CUBE" strategic framework.

Jangseok Choi stated that the strategy revolves around four core priorities: capacity, utilization, bandwidth, and efficiency.

In terms of capacity, Samsung plans to expand storage vertically to increase storage density without increasing the footprint of printed circuit boards (PCBs).

In terms of utilization, the company positions the value of 3D memory beyond simply stacking layers, focusing on optimizing the logic and storage architecture to reduce latency.

In terms of bandwidth, Samsung plans to replace the horizontal data path with a vertical high-speed channel to shorten the distance between chips;

In terms of efficiency, the focus is on power consumption and thermal management, minimizing the energy consumption per bit of data transmission and maximizing performance per watt.

The introduction of the CUBE framework signifies that Samsung is attempting to coordinate the R&D direction of next-generation storage products with a systematic architectural approach, rather than simply seeking breakthroughs in individual metrics.

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