SanDisk’s new patent revealed: processor directly bonded to NAND flash chip, HBM relegated to auxiliary role

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SanDisk is driving a fundamental reconstruction of storage architecture—directly bonding computational units with NAND flash memory, and relegating HBM’s role from core memory to an auxiliary tier.

According to patent documents published by the US Patent and Trademark Office, SanDisk proposes a 3D stacked architecture that directly integrates multi-core processors onto CBA storage chips, all packaged on the same interposer layer, with HBM distributed around the periphery of this stacked structure. This design aims to simultaneously break through HBM’s capacity ceiling and overcome the limitations of existing high-bandwidth flash (HBF) architectures in latency, power consumption, and system integration.

The exposure of this patent shows that as SanDisk accelerates the mass production route for HBF, it is also laying out more aggressive memory-compute fusion solutions at the patent level, which may have a profound impact on AI accelerator and GPU memory architecture design paths.

HBM Capacity Bottleneck Spurs New Architectural Exploration

HBM, leveraging its high bandwidth, has become the mainstream memory solution for current AI chips, but its capacity limitation is increasingly becoming a restricting factor. According to Wccftech technology media, current HBM solutions typically offer single-stack capacities of 32 to 64GB, which is difficult to meet the continuously growing memory demands of large-scale AI models.

To address this, SanDisk previously launched the HBF architecture, borrowing HBM’s vertical stacking concept, using through-silicon vias (TSV) to interconnect multiple layers of NAND flash, forming a unified storage stack. As disclosed by SanDisk, a single HBF stack can scale up to 4TB, with bandwidth approaching HBM levels, and at the same cost, capacity can reach 8 to 16 times that of HBM.

However, aside from its capacity advantage, NAND flash still has inherent shortcomings. Wccftech points out that NAND is physically farther from the compute core in system architecture, and its data access speed is slower than DRAM-based architectures; this structural disadvantage limits HBF’s applicability in latency-sensitive workloads.

Core of the New Patent: Direct Bonding of Compute and NAND

The latest SanDisk patent proposal is a direct response to the above latency issue. According to the patent documents, the design places a NAND flash chip built on a CBA structure directly underneath the compute chip (such as an AI accelerator or GPU), enabling direct physical bonding between the processor and NAND.

The CBA structure itself merges a high-capacity NAND flash array with a CMOS logic layer; the entire integrated stack is then installed on an interposer. The HBM chip stack is attached to one or more sides of this combined stack, sharing the same interposer platform with the NAND layer.

The key to this architecture lies in redefining the boundaries between different storage media: HBM handles immediate, high-speed memory operations, while the NAND flash layer undertakes read/write-intensive workloads and massive data storage tasks. According to Wccftech, in this setup, HBM is still integrated into the system, but its role shifts from dominance to serving as a specific functional module within the overall storage-compute hierarchy.

Parallel Deployment Beyond HBF

It’s worth noting that the architectural direction outlined in the above patent is not a replacement for SanDisk’s current focus on HBF, but a parallel advancement in technological reserves. SanDisk is still accelerating development of HBF, with HBF representing its primary commercial bet for near-term, high-capacity storage solutions.

The processor-direct-to-NAND 3D stacked scheme described in the new patent points to a longer-term architectural evolution, aiming to fundamentally shorten the physical distance between compute units and high-capacity storage, thereby optimizing bandwidth, latency, and energy efficiency at the system level.

For AI chip designers and packaging technology supply chains, SanDisk’s patent deployment sends a clear signal: deep integration of storage and compute is moving from concept to specific technological pathways, and the ecological competition around interposer packaging platforms may further intensify.

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