SemiAnalysis: Google's next-generation TPU will use Intel's EMIB-T packaging

On July 1st, according to renowned semiconductor analytics firm SemiAnalysis, Google's next-generation TPU, codenamed Humufish, will abandon TSMC's CoWoS packaging and instead adopt Intel's EMIB-T technology.

Currently, TSMC's CoWoS is the industry's default standard for AI chip packaging. As a leading tech giant, if Google successfully migrates its flagship product to Intel's packaging system, it will impact TSMC. SemiAnalysis stated on Platform X,

"Google’s next-generation TPU, codenamed Humufish, will use Intel EMIB-T instead of TSMC CoWoS. CoWoS is the default industry choice, so the shift of a flagship component to another solution is worth attention."

The core difference between the two lies in the physical paths of the packaging. CoWoS places all dies on a large silicon or RDL interposer, while Intel’s EMIB technology embeds small silicon bridges directly into the organic substrate, only bridging where die-to-die connections are needed.

Breaking Photomask Limits and Reducing Costs

TSMC’s CoWoS silicon interposer is printed using lithography, so its physical size is strictly constrained by photomask limits.

SemiAnalysis explained: "The limit for the monolithic version (CoWoS-S) is about 3.3 times the photomask size, which is why TSMC shifted to CoWoS-L. EMIB is not constrained by photomask limits, making it a much more scalable technology."

Beyond size, cost and efficiency are also core drivers. EMIB completely eliminates the expensive interposer, significantly reducing packaging costs.

The difference is most intuitively reflected in silicon utilization. Wafers are round, and cutting large interposers from them leads to a lot of waste around the edges—the larger the size, the lower the yield. It’s like cutting large square cakes from round dough, with much leftover scrap at the corners.

In contrast, SemiAnalysis stated: "Tiny silicon bridges can be densely arranged with almost no waste." Additionally, this choice offers buyers a second supplier outside TSMC.

Vertical Power Supply, EMIB-T Suited for Next-Generation HBM

Humufish specifically uses EMIB-T technology, where the "T" stands for Through-Silicon Via (TSV). This design solves the power delivery challenges of conventional packaging.

SemiAnalysis explained, standard EMIB has no vias in the silicon bridge, so power must bypass it through the substrate, putting strain on power delivery. "EMIB-T delivers power directly vertically through the silicon bridge and adds capacitors and ground layers to provide purer power."

This architecture upgrade is meant to enable the chip to adapt to next-generation HBM (High Bandwidth Memory) and greater bandwidth interconnect needs.

Architectural Adaptability and Mass Production Test

Addressing market discussions about TSMC's CoWoS-L also using localized silicon bridges, independent analyst Nutty pointed out that CoWoS-L adds a global RDL layer atop the silicon bridge structure, which improves wiring flexibility but increases area and process complexity.

"For chips like Humufish, seemingly optimized for inference and agent workloads, the data flow is likely more structured," Nutty analyzed. "In this case, EMIB’s approach of putting high-density links only where needed is more rational than paying for wiring flexibility across the entire package."

Nutty believes this is the key significance of EMIB-T. It not only uses less silicon and cuts packaging costs, but also provides a second supplier outside the closed CoWoS ecosystem.

Yield Rate is Critical, Intel Faces Execution Test

Although the architecture is highly attractive, execution remains the biggest unknown. User Axi bluntly said: "Show us the yield rates before boasting about cost savings."

SemiAnalysis warned: "Standard EMIB has shipped at scale for years, but EMIB-T is a new technology and silicon bridges delivering power are far more difficult to scale up in manufacturing."

Only if Intel can improve yield and output as planned will these advantages be realized. If Intel’s progress is delayed, Google’s backup plan remains the capacity-constrained CoWoS. The success or failure of this technological migration will directly test Intel's actual delivery capability in advanced packaging.

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