The battle for advanced production capacity is heating up! Bank of America: Exploding demand for server CPUs will further squeeze TSMC's supply of advanced process capacity.

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The server CPU market is experiencing a structural boom and is set to deeply reshape the landscape of the Asian semiconductor supply chain.

According to Zhuifeng Trading Desk, a recent research report from Bank of America Securities indicates that as AI workloads shift from training to inference and agentic AI applications, server CPU demand is surging rapidly, further occupying TSMC's advanced 5nm and 3nm process capacities, exacerbating the already tight wafer foundry market.

Bank of America estimates that the total addressable market (TAM) for global server CPU semiconductor manufacturing will expand from about $15 billion in 2025 to about $49 billion in 2028, at a compound annual growth rate (CAGR) of 49%.

Meanwhile, AMD and hyperscale cloud vendors leveraging ARM-based CPU solutions continue to gain market share, driving the outsourced production penetration rate from 52% in 2025 to 71% in 2028, opening up significant incremental space for Asian supply chain companies such as TSMC and ASE.

The report suggests that the surge in server CPU demand will push TSMC’s capital expenditure for 2027 up to $75-80 billion, simultaneously driving advanced packaging capacity demand (CoWoS) to expand at a 52% CAGR, making ASE and other packaging and testing companies key beneficiaries.

The Rising Role of CPUs: From GPU Sidekick to AI Infrastructure Core

According to the BoA report, AI infrastructure over the past few years has been dominated by GPUs and custom AI accelerators, with CPUs playing only a supporting role—handling data pre-processing, storage access management, and scheduling. However, as AI moves from the training stage to production inference, enterprise deployment, and agentic workflows, the strategic importance of CPUs increases significantly.

During AI inference, the model loading stage relies on disk I/O, memory movement, and CPU speed; the scheduling in decoding, per-token control flow, memory management, and KV cache routing are all highly CPU-dependent. The rapid proliferation of agentic AI further amplifies this demand—agents need to plan sub-tasks, retrieve context, call tools, manage state, and perform iterative operations, all of which are highly sequential, latency-sensitive, branch-intensive, and I/O-intensive—naturally best suited for CPUs.

BoA’s semiconductor analyst Vivek Arya expects that the global server CPU market TAM will expand from about $35 billion in 2025 to over $170 billion in 2030 at a CAGR of 37%. Of this, AI server CPUs’ share will rise from 52% in 2025 to over 83% in 2030, becoming the core growth driver.

Outsourcing Wave Reshapes Supply Chain: AMD and ARM Accelerate Intel Share Gains

The server CPU manufacturing landscape is undergoing profound transformation. BoA notes that before 2018, Intel dominated server CPU production with its IDM (integrated device manufacturer) model, and the TAM for outsourced manufacturing was only about $112 million. The turning point came in 2019, when AMD outsourced EPYC Rome processors to TSMC’s 7nm process, leading to significant performance improvements. AMD continued to erode Intel’s market share, driving outsourced CPU manufacturing TAM to grow at an 83% CAGR to $770 million by 2025.

Looking ahead, BoA expects AMD to continue to outperform Intel in the x86 market due to a superior process roadmap. Meanwhile, ARM-based server CPUs—whether commercial offerings like AMD Venice and Nvidia Vera, or custom chips from hyperscalers such as AWS Graviton 5, Google Axion, and Microsoft Cobalt—will all grow rapidly from a low base. BoA expects the outsourced server CPU manufacturing market to grow at a 65% CAGR to $34 billion by 2028.

For specific products, AMD Venice server CPU supply chain output is expected to grow from 2.8 million units in 2026 to 8.7 million units in 2027; Nvidia Vera CPU output in 2026/2027 is forecast at 3.6 million and 9.4 million units respectively; Google Axion CPU, with a 2:1 CPU to server motherboard configuration, is projected to expand output to 1.8 million units in 2026 and over 5.5 million units in 2027.

TSMC Advanced Process Faces Supply Pressure: 5nm and 3nm Utilization Remain High

The boom in server CPU demand will directly intensify the supply crunch for TSMC’s advanced processes. BoA estimates server CPU-related wafer consumption will rise from 16,000 wafers per month in 2025 to about 50,000 in 2028, representing 13% of TSMC’s 5nm and below node wafer usage (compared to just 6% in 2025).

BoA expects TSMC’s server CPU revenue contribution from major clients to grow from 1% in 2020 to 8% in 2026, and further to 12% in 2028, mainly driven by the rapid ramp-up of AMD Venice, Nvidia Vera, and custom ARM CPUs from hyperscale cloud vendors.

In terms of production planning, BoA expects TSMC’s 7nm and below capacity to increase from 320,000 wafers per month in 2023 to about 680,000 in 2028, with a CAGR of 16%. At that point, advanced process capacity will account for 40-45% of total capacity. The 3nm node, as the core for high-performance computing, networking, and flagship smartphone chips, will maintain near-full utilization even as capacity expands, supporting continuous price increases for TSMC.

BoA expects TSMC’s capital expenditure to reach $76 billion in 2027, and further rise to $81 billion in 2028, with a CAGR of 21% from 2026 to 2028. Despite the significant capex growth, gross margins are still expected to expand to 68% in 2028, as the depreciation growth rate (17% CAGR) trails revenue growth (28% CAGR).

Based on these considerations, BoA maintains its Buy rating for TSMC, raising the target price from NT$2,560 to NT$3,060 (ADR target price from $490 to $590), and raising 2026/2027/2028 EPS forecasts to NT$103/150/177 respectively.

Advanced Packaging Demand Surges: CoWoS Expansion Pressure Multiplies

Server CPUs in the AI era demand much higher standards for advanced packaging. Nvidia Vera and AMD Venice both adopt CoWoS packaging; many x86/ARM CPUs use chiplet architectures; and test cycles are significantly prolonged due to the complexity of chip probing, final testing, aging tests, and system-level tests (SLT).

BoA estimates that server CPU packaging and testing TAM will grow from about $1.9 billion in 2025 to $9.6 billion in 2028 at a CAGR of 71%, accounting for 24% of TSMC, ASE, and Amkor’s advanced backend businesses (compared to just 11% in 2025).

To meet the combined packaging demand from GPUs, ASICs, and server CPUs, BoA expects the industry’s CoWoS capacity should expand at a 52% CAGR.

TSMC will lead the expansion, increasing CoWoS capacity from 120,000 wafers per month in Q4 2026 to 180,000 in Q4 2027, maintaining a 63% supply share; ASE’s capacity share will rise from 18% in 2026 to 29% in 2027, becoming an important second source, with its LEAP business expected to grow to about $12 billion by 2028 (CAGR 96%).

In the 3D packaging field, copper-to-copper hybrid bonding is becoming the next key node for performance improvement.

AMD has validated this roadmap via 3D V-Cache, and its sixth-generation EPYC Venice processor will combine TSMC’s SoIC-X and CoWoS-L technologies; Nvidia expects to use this solution on its Feynman GPU in 2028; Google is also in early conversations with the supply chain regarding custom server CPUs using multi-chip stacking. BoA expects TSMC’s SoIC capacity to grow from 20,000 wafers per month in Q4 2026 to 35,000 in Q4 2027, and further to 50,000 in Q4 2028.

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