The real bottleneck in CPO mass production: not manufacturing, but testing

As the computing power expansion of AI data centers pushes CPO toward mass production, a neglected link is becoming the bottleneck of the entire industry chain—testing.

With the ongoing expansion of AI data center scale, traditional copper interconnects are approaching their physical limits. Co-Packaged Optics (CPO) is regarded by the industry as one of the key interconnect solutions for next-generation AI infrastructure. TSMC’s COUPE platform is expected to enter mass production in 2026, marking CPO’s transition from laboratory to commercialization.

However, CPO's inspection and testing stages remain a difficult threshold to cross. The industry currently lacks unified standards, and processes are highly reliant on manual labor. This makes testing one of the main bottlenecks restricting the large-scale mass production of CPO chips. TrendForce recently published a systematic study on this issue.

Why is CPO testing so difficult?

To understand this issue, you must first understand the structure of CPO.

CPO integrates optical components into the photonic integrated circuit (PIC), and then co-packages them with the electronic integrated circuit (EIC) in a single chip, replacing electrical paths with optical routes to reduce power consumption and latency. The component formed by bonding PIC and EIC is called the Optical Engine (OE).

Traditional EIC testing is purely electrical, while the PIC contains numerous optical components, such as couplers, modulators, photodetectors, optical filters, and optical waveguides. Testing an OE requires expertise in electrical, optical, and optoelectronic interaction, making it far more complex than traditional chip testing.

PIC testing requires measurement of insertion loss (IL), polarization-dependent loss (PDL), responsivity, waveguide propagation loss, optical crosstalk, and other parameters—none of which currently have unified testing standards.

There is also a more specific physical challenge: accurate alignment of optical probes.

The process of coupling external light from optical fibers into OE waveguides is called optical coupling. The cross-sectional area of single-mode fiber core is about 78.5 square micrometers, while the waveguide cross-section is only about 0.099 square micrometers—a difference of nearly 800 times. Without nanometer-level alignment precision, the coupling loss will be tremendous.

This means the fiber array must maintain accurate spacing from the wafer or chip surface while tweaking the coupler angle to maximize optical power transmission, and then scan different wavelength ranges. Currently, this process is still manually performed.

The result: 100% inspection of a single PIC chip takes an average of over 100 seconds. This is one of the central bottlenecks for CPO chip mass production.

“EIC Test vs. PIC Test Table”—Comparison of testing principles, alignment precision, industry maturity, and probe card vendors. Image source: TrendForce, same below

Four Testing Stages: Which is the Most Critical Step?

A CPO chip needs to pass through four testing stages from wafer to system:

Stage One: PIC wafer-level testing (OWAT)—DC electrical and basic optical testing, including measurement of optical power, loss, dark current, and other basic optical parameters.

Stage Two: EIC-PIC wafer-level testing—Modulation function tests (electro-optic, optoelectronic, optical-optical), high-speed testing, and S parameter measurement.

Stage Three: OE-level testing—Full process calibration, DC testing, high-speed testing, optical circuit testing, and S parameter measurement. This is the key stage for confirming "Known Good Optical Engine" (KGOE).

Stage Four: Advanced packaging module-level testing—Full system function validation and optical circuit testing.

Among the four stages, the most critical is the first stage: PIC wafer-level testing.

The logic is straightforward: The PIC is usually manufactured with mature processes, while the EIC uses advanced processes with high costs. If defective products can be filtered out at the wafer stage before PIC is bonded to EIC, expensive EICs are not wasted on problematic PICs, significantly reducing losses in later steps.

This is like quality inspection along a production line—the earlier a problem is found, the smaller the loss.

"CPO Manufacturing Process and Testing Stage Diagram"—a complete process flowchart from wafer acceptance testing to system-level testing

Equipment Vendor Landscape: Giants Make Up Shortcomings, New Players Enter

The CPO testing equipment market is accelerating its formation, with integration between traditional ATE (Automated Test Equipment) giants and professional optical testing vendors as the main storyline.

Advantest and FormFactor

The traditional EIC testing market is dominated by Japan’s Advantest and America’s Teradyne. CPO testing requires both EIC and PIC capabilities, so the two giants both chose to partner with professional optical probe vendors to cover their deficiencies.

Advantest partnered with FormFactor. In June 2024, Advantest, together with Jenoptik and Ayar Labs, launched the UFO probe card, integrating electrical and optical probes in one card for simultaneous electrical-optical testing. Its core innovation is alignment tolerance compensation—by specially shaping the probe’s output beam, even if probe positioning has slight errors, the optical signal still enters the PIC coupler, dramatically reducing alignment time.

In April 2025, Advantest and FormFactor launched the V93000-Triton photonic test system, equipped with 9-axis photonic alignment and FormFactor’s OptoVue Pro optical alignment system. Its CalVue technology observes the fiber array via a specially designed retro-reflector and uses automatic machine vision algorithms to calibrate Z-axis displacement and optical positioning in real time, further reducing fiber alignment time.

Teradyne and ficonTEC

Teradyne took a dual approach of acquisition and collaboration. In 2025, Teradyne acquired Quantifi Photonics and partnered with Germany’s ficonTEC (now a subsidiary of China’s Robo Technik).

In March 2025, the two launched the industry’s first high-volume 300-mm double-sided wafer probe test system. ficonTEC provided the WLT-D2 double-sided wafer test platform with 50-nm precision alignment, able to perform electrical tests on the wafer top and optical tests on the underside simultaneously, boosting test efficiency. Teradyne provided UltraFLEXplus ATE and IG-XL system software.

Subsequent DLT-D1 is a double-sided chip-level test system, capable of connecting up to three parallel test heads to increase throughput and lower test costs. With this, ficonTEC has formed a complete CPO test product line from wafer level to chip level.

Keysight

Keysight, a global leader in measurement instruments, also provides comprehensive PIC wafer test solutions, integrated with FormFactor and compatible with FormFactor’s Velox probe control software.

Keysight’s N778x series polarization synthesizers provide fast switching between different polarization states (SOP), together with N7700100C polarization Lambda scanning software, to deduce IL, PDL, TE/TM IL parameters via matrix methods. This setup requires no polarization-maintaining fibers nor manual pre-calibration of polarization at multiple wavelengths, greatly improving testing efficiency. Its SOP locking technology can fix the input light polarization to a designated point, ensuring coupling stability throughout the wavelength scan.

Chroma

Chroma is a global leader in system-level test (SLT) equipment. Its Model 58604/58604-C/58606 series for photodiode aging and reliability testing is specially designed for 3D sensor devices, lasers, photodetectors, modulators, and other PIC components. Model 58606 provides 256 SMU channels per module layer, configurable up to 7 layers, totaling 1,792 channels. Chroma has announced it will leverage its optical testing expertise at the SLT stage to develop CPO test equipment.

Enlitech

In September 2025, Enlitech and iST launched the Night Jar silicon photonics chip test platform. This is an add-on hyperspectral imaging analysis system that can be directly mounted on any brand of probe station, suitable for WAT, CP, FT, and other test stages.

Night Jar addresses a long-term industry pain point: previously, light leakage in waveguides could only be roughly estimated via reflected light, providing only overall or average loss values. Night Jar precisely locates leakage sites and measures quantitative IL for specific waveguide sections or optical components, supports wafer-level optical loss mapping, and enables researchers to identify defects faster and more accurately, ultimately increasing production yield.

"CPO Test Equipment Supply Chain Panorama Table"—shows the distribution of suppliers covering optical probes, measurement instruments & systems, and automatic test equipment

The Market Opportunity Window is Opening

Chip design is becoming increasingly complex. SoC testing is getting harder. The required number of test stations and total test time per chip are rising, and the proportion of test equipment in semiconductor capital spending is increasing accordingly. As CPO chips are added to product lineups, this proportion is expected to rise further.

The CPO test equipment market is taking shape. From the perspective of vendors, traditional automatic test equipment giants Advantest and Teradyne are rapidly supplementing their optical capabilities through acquisitions and partnerships, while Keysight, Chroma, Enlitech, etc., occupy positions in their respective niche fields. The entire supply chain—optical probes, measurement instruments, and automatic test equipment—is reorganizing around the demands of CPO testing.

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