This year's Semiconductor highlights: Advanced packaging evolves towards 3D system integration; CPO manufacturing bottlenecks lie in testing...

With the continuous expansion of AI computing power, the logic of semiconductor capacity expansion is extending from chip and wafer manufacturing to advanced packaging, optical interconnects, and testing. During SEMICON Taiwan 2026, research by Citi, Nomura, and UBS revealed six highlights of this year's exhibition: advanced packaging is upgrading to 3D system integration, CoWoS continues to expand and is shifting to OSAT, CPO is accelerating mass production, testing is becoming a new bottleneck, the delivery time of key equipment is lengthening, and the AI ASIC ecosystem is further maturing.

The three institutions each have their own focus. UBS focuses on TSMC's 3D Fabric and advanced packaging capacity expansion , raising its CoWoS capacity forecast for the end of 2027 to 260,000 wafers/month; Citi focuses on the CPO manufacturing process , paying particular attention to active coupling and automated bonding; Nomura, on the other hand, focuses on testing and equipment , believing that testing after EIC/PIC bonding may become a bottleneck for CPO mass production, and has found that the delivery time for some equipment has been extended to two years.

From an industry trend perspective, advanced packaging is evolving from single packaging technologies to 3D system-level integration, and the core challenge for CPOs (Consumer Product Owners) is shifting from technology verification to large-scale manufacturing and testing. As AI chip performance improves, the importance of packaging, optical interconnects, and testing continues to rise, and the industry chain is expanding towards the downstream.

At the same time, capacity constraints such as equipment and factory space are beginning to emerge, and AI ASICs are becoming a new growth point. Overall, the research from the three institutions points to the same change: the expansion of AI semiconductor production is shifting from "front-end capacity expansion" to "full-chain capacity expansion," with packaging, CPO, testing, and equipment expected to become key links in the next stage.

TSMC Circuit Diagram: From CoWoS to 3D System Integration

At the exhibition, TSMC systematically showcased its 3DFabric roadmap for addressing the growth of AI computing power, with advanced packaging and optical interconnects being two key themes.

According to a UBS report, TSMC's 5.5x size CoWoS mask has achieved mass production with a yield of over 98%; in 2028, it will further expand to 14x size mask and support 20-layer HBM stacking, and in 2029 it plans to further support 24-layer HBM.

Panel-level packaging is also progressing rapidly. UBS points out that equipment suppliers are gaining confidence in the mass production of TSMC's CoPoS (310×310mm²). TSMC aims to complete process and equipment selection by mid-2027 and achieve mass production in 2028.

It's worth noting that TSMC appears to be taking a more cautious approach to its CoWoS capacity expansion in the second half of 2027, with some CoW outsourcing work potentially being handled more by ASE (Application Service Provider). This also means that advanced packaging capacity expansion is further spilling over from TSMC to OSAT (Outsourced Semiconductor Assembly and Test) vendors.

Optical interconnects represent another path for TSMC's 3D Fabric to extend towards system-level integration. UBS states that TSMC's COUPE roadmap aims to achieve 200G/channel by 2026 and increase to 400G/channel by 2030.

The core contradiction behind this is that the growth rate of AI computing power is gradually outpacing the increase in system I/O bandwidth. A TSMC speaker pointed out that AI computing demand is growing at a rate of approximately three times every two years, while I/O bandwidth is only growing at a rate of about 1.4 times. As transmission frequencies and distances continue to increase, the limitations of copper interconnects are becoming increasingly prominent, making optical interconnects a crucial direction for solving system-level communication bottlenecks.

CPO Manufacturing: Testing Becomes a Key Bottleneck for Mass Production

As CPO moves from technology verification to large-scale mass production, the challenges facing the industry chain are changing: the question is no longer just "can it be done", but "can it be done stably and efficiently".

Citigroup points out that CPO manufacturing involves the integration of multiple components such as EIC, PIC, lenses, and fiber/FAU, among which active coupling requires real-time optical power feedback and multi-axis positioning. Once mass production begins, the industry still needs to further improve alignment speed, parallel processing capabilities, and the level of automated bonding.

Testing has become another major bottleneck. Nomura is focusing on Insertion 2, the testing phase after the EIC and PIC complete wafer bonding. Due to the current low testing throughput, the industry chain has begun discussing whether this step can be skipped.

However, Nomura believes that while eliminating Insertion 2 can shorten the production cycle, some testing items cannot be covered by subsequent stages. Therefore, this step still helps to determine wafer yield and clarify supply chain responsibilities. In other words, the trade-off between testing efficiency and testing coverage is becoming a problem that CPOs must solve in mass production.

UBS predicts that the industry may gradually simplify Insertion 2 while increasing its reliance on Insertion 3—specifically, single optical engine testing. At the exhibition, Chroma Electronics, a testing equipment manufacturer, suggested that CPO testing may shift towards a "shift-to-middle" approach: for high-density extended-scale switches, a defect in any optical engine could lead to the scrapping of the CoWoS-level package; therefore, 100% known good verification of Insertion 3 may become a necessary condition for mass production.

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