TSMC Investor Top 10 Questions Explained: AI Demand, Capacity Expansion, and Competitive Landscape

```

With Tesla's announcement of its TeraFab self-built chip factory plan as the latest landmark event, combined with concerns over liquefied natural gas supply triggered by the Middle East situation and Intel and Samsung's gradual catching-up in process technology, the competitive and supply chain environment faced by TSMC is becoming increasingly complex.

According to Wind Chasing Trading Desk, JPMorgan responded systematically to the ten most pressing investor questions in its latest research report dated March 24, covering capital expenditure trajectory, capacity planning, competitive landscape, packaging strategy, and supply chain risks, providing the market with a comprehensive fundamental evaluation framework.

JPMorgan maintains its Overweight rating for TSMC, setting the target price at NT$2,250. The bank expects TSMC’s USD revenue to grow by over 30% in 2026, driven by strong N3 demand, accelerating N2 capacity ramp-up, expansion of advanced packaging business, and a significant increase in blended average selling price.

In the latest AI revenue growth forecast, TSMC has raised its guidance for compound annual growth rate of AI revenue from mid-40% to mid-high 50% for 2024–2029. Meanwhile, JPMorgan expects capital expenditure to potentially exceed $60 billion in 2027, further approaching $70 billion in 2028.

Capital Expenditure Surges, Capacity Ramp-Up Cycle Lengthens

JPMorgan believes TSMC’s capital expenditure is entering a new upward inflection point. Guidance for 2026 at $52–56 billion is a significant increase from previous years, and the company has clearly stated that capital expenditure over the next three years will be "significantly higher" than the past three years. According to the bank’s estimates, capacity growth rate will accelerate from the previous 4–5% to high single digits or about 10%.

Capacity expansion spans multiple nodes and regions:

N3 nodes include Tainan Fab 18 P9 in Taiwan, Arizona P2, and Japan P2;

N2 nodes are mainly laid out in Kaohsiung P1–P5, and potentially Tainan Fab 18 P10–P12 in Taiwan;

A14/A10 nodes correspond to Kaohsiung P6–P8 and Taichung plant in Taiwan;

TSMC also plans a brand new eighth phase in Tainan for A10 and future process nodes.

It is noteworthy that the cycle from capital expenditure to actual capacity release is lengthening. JPMorgan points out that current spending for the most advanced nodes may not translate into effective capacity until 2028 at the earliest—because the wafer count per unit clean room area for N2 is lower than N3, and the construction cycle is longer.

Regarding market concerns about whether TSMC might cede market share to competitors due to conservative expansion pacing, JPMorgan's judgment is: overall market share risk is limited.

The bank analyzes that chip design cycles require at least two to three years, with an additional one to two years to ramp up mass production at a specific foundry, making the overall switch cycle three to five years and conversion costs extremely high.

From a technology competitiveness perspective, the bank estimates that Intel’s 18A currently matches TSMC’s N3E level, while Samsung’s 2nm is roughly equivalent to TSMC’s 3nm, still about a generation behind. TSMC’s N2 has already entered mass production, while Intel's 14A PDK v1.0 is expected at the earliest by year-end 2026, keeping TSMC in a roughly two-year lead in advanced process nodes.

JPMorgan acknowledges that due to persistent tightness in advanced process capacity, Samsung's cooperation with Tesla and Intel's with CSPs will continue to attract market attention, but believes their actual impact on TSMC’s share will be limited.

Packaging Strategy Shifts, Outsourcing Ratio Rises

Regarding advanced packaging, JPMorgan believes TSMC sees it as an "enabler" to drive front-end wafer sales rather than an independent profit growth driver, which will give TSMC more flexibility in its outsourcing strategy.

Specifically, the On-Substrate (oS) process in CoWoS is expected to be fully outsourced to ASE, and CoW orders are gradually shifting to outsourced packaging and testing factories (OSAT). JPMorgan also points out that advanced packaging does not constitute a springboard for competitors like Intel to enter front-end wafer foundry.

Looking ahead, TSMC’s strategic focus will pivot to CoPoS and 3D-SoIC. As NVIDIA may introduce 3D stacking in its Feynman architecture, and multiple ASIC clients migrate to N2-based 3D-SoIC, expansion of 3D-SoIC is expected to be the next key stage.

Due to land and clean room resource constraints, the priority between advanced packaging and advanced process will tilt toward the latter, which will further boost OSAT outsourcing ratio over the next two to three years.

Tesla TeraFab Impact?

Elon Musk recently announced the TeraFab plan, aiming to establish a domestic AI chip production system with annual capacity of 1 terawatt, covering logic, memory, and advanced packaging. JPMorgan believes the probability of TeraFab posing substantive impact to TSMC is currently low.

The bank outlines three major obstacles:

First, advanced process technology is highly concentrated, currently only TSMC, Intel, and Samsung have production-proven advanced nodes, while IBM only provides laboratory-level process roadmaps;

Second, transitioning from process R&D to mass production requires massive engineering accumulation, involving devices, EDA, materials, chemicals, and each of hundreds of manufacturing steps incurs yield costs;

Third, a 100,000 wafer/month N2 fab requires $50–60 billion current investment, with continuous R&D needed to maintain technical leadership across process generations.

JPMorgan points out that technological innovation in semiconductors (such as FinFET, GAA, EUV, etc.) typically takes 15–20 years from lab to mass production; whether this cycle can be drastically shortened is a key factor. While Musk has a track record of excellent execution, the bank thinks disrupting the status quo might require truly new breakthroughs at the physical layer.

Capacity Node Planning and EUV Equipment Procurement

In terms of specific capacity figures, JPMorgan estimates N3 capacity may reach 165,000–170,000 wafers/month by year-end, higher than the previous baseline forecast of about 150,000 wafers/month, mainly benefiting from cross-plant operations using Fab 15 (N7 and 28nm) and early introduction at Fab 18 P9.

Looking to 2028, with Fab 18 P9 fully ramped, Arizona P2 entering mass production in the second half of 2027, plus Japan P2 and new plants (Fab 18 P10–P12), total N3 capacity is expected to surpass 200,000 wafers/month.

For N2, capacity by year-end 2026 is estimated at about 100,000 wafers/month, and expected to expand to 200,000–240,000 wafers/month over the next three years, mainly from Kaohsiung P1–P5 and Arizona P3.

On EUV procurement, JPMorgan expects TSMC to purchase 29–31 units in 2026, up from 21–23 units in 2025. Critically, High-NA EUV equipment will not be used for N2, A16, or A14 nodes and is expected to be introduced at the A10 node (around 2030–2031) at earliest.

Gross Margin Outlook and Supply Chain Risks

JPMorgan expects TSMC’s gross margin in 1H 2026 to reach the high-60% to 70% range, benefited by strong advanced process demand, higher proportion of expedited orders (hot-run and super hot-run), favorable NT$ exchange rate, and continued conversion of idle N7 and 28nm capacity to advanced nodes. Depreciation expenses are also expected to grow slower than revenues (19% in 2026 vs. >30% revenue growth).

On risks, Taiwan relies on LNG for about 48% of power generation, with about 33% imported from Qatar and local storage capacity of only about 11–15 days.

With Middle East tensions, higher energy costs will be the main pressure on gross margin in 2H 2026, with peak risk concentrated in August–September summer power demand season. JPMorgan believes given the semiconductor industry’s strategic importance, the actual probability of production interruption is low, and industrial power supply is likely to be prioritized in Taiwan.

Regarding shortages of specialty gases like helium, JPMorgan's research shows TSMC currently holds over a month of inventory, is actively sourcing from alternative channels (with price premiums of 2–4 times), and is improving gas recovery utilization rates, and is expected to safely navigate through supply pressures.

Blended Average Selling Price Expected to Trend Higher

On pricing, JPMorgan believes recent market reports of price hikes actually refer to a 6–10% increase already negotiated for 2026 for leading-edge nodes (signed in Q3 2025, effective January 2026), and do not indicate a new round of widespread price increases.

However, blended average selling prices continue to rise—higher proportion of expedited orders (50%/100% premium), HPC customers becoming main drivers for N3 demand, and more clients preferring multi-year pricing agreements together propel TSMC’s blended average price up about 20% for 2026.

For co-packaged optics (CPO), JPMorgan believes CPO’s direct revenue contribution to TSMC will be limited, as related build modules cost far less than advanced process wafer ASP (HPC N3 wafers about $26,000–$30,000), while OSAT partners and test ecosystem will be major beneficiaries as CPO begins volume.

Based on about a 20X 12-month forward P/E, JPMorgan sets TSMC’s target price for December 2026 at NT$2,250, higher than the five-year historical average, reflecting the bank’s positive view of continued AI-driven fundamentals.

Risk Warning and DisclaimerThe market has risks, and investment requires caution. This article does not constitute personal investment advice, nor does it consider an individual user's special investment objectives, financial situation, or needs. Users should consider whether any opinions, views, or conclusions herein fit their specific circumstances. Investment based on this is at your own risk. ```