TSMC PIC production capacity expands 30 times in three years, CPO supply chain enters volume release window

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The leapfrog expansion of TSMC’s photonic integrated circuit (PIC) capacity is pushing CPO (co-packaged optics) from the laboratory phase to large-scale mass production, opening a new growth window for the entire AI optical communication supply chain.

According to Taiwan’s Industrial and Commercial Times on Wednesday, brokerage institutions estimate that TSMC’s PIC monthly capacity will rapidly increase from the current approximately 500 wafers to 10,000 wafers by the second quarter of 2026, 15,000 wafers by the fourth quarter, and further to at least 25,000 wafers in 2028, expanding more than 30-fold in three years.

Based on 648 dies per wafer, the annualized PIC output will soar from about 4 million units to nearly 194 million units, with actual optical engine shipments estimated to reach 48.6 million units.

The direct beneficiaries of capacity expansion will first be the top-tier customers. Brokerages predict that from 2026 to 2027, the main mass production customers of TSMC’s COUPE platform will be Nvidia, Broadcom, and AMD; after capacity is further released in 2028, customers like MediaTek, Marvell, and Ayar Labs are also expected to have their CPO projects included on the mass production platform. At the same time, the demand for downstream sectors such as FAU, lasers, optical testing, probe cards, test sockets, and automation equipment will rise in tandem as PIC output ramps up.

Behind the triple jump in capacity: AI computing power drives a surge in optical engine demand

PIC is the core component of CPO optical engines, responsible for the conversion, guidance, and coupling between electrical and optical signals. As AI server clusters continue to expand and switch bandwidth evolves from 25T and 50T to 100T and 200T, the demand for optical engines is rising accordingly, making progress on TSMC’s COUPE platform a key market focus.

Brokerages point out that this round of PIC capacity expansion at TSMC has three strategic significances:

First, it signals that CPO is officially moving from the experimental and small-batch verification stage to the mass production preparation phase;

Second, the deep integration of silicon photonics and advanced packaging will enable COUPE, SoIC, and CoWoS to jointly form a more complete AI optoelectronic integration platform;

Third, PIC ramp-up will drive increased demand across the entire supporting supply chain, covering segments such as FAU coupling, lasers, optical testing, and automation equipment.

Multiple process bottlenecks remain; ramp-up pace still uncertain

Although the capacity expansion path is clear, brokerages also caution that increased PIC capacity does not mean CPO will immediately scale up in full. After PIC wafers are completed, several subsequent steps are required, including SoIC integration, optoelectronic testing, optical engine packaging, FAU coupling, and system-level verification. Each stage poses potential yield and process timeline risks.

According to brokerage estimates, assuming a 50% yield for SoIC, a monthly capacity of 10,000 wafers corresponds to an optical engine output of about 2 million units; after accounting for downstream assembly yield losses, actual shipments will be further narrowed to around 390,000 units.

This means that between wafer capacity and end shipments, there is significant yield attrition. The ability of each supply chain segment to improve yields will largely determine the actual scale and pace of CPO ramp-up.

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