TSMC's 2nm production capacity in crisis: Apple secures the first batch, AMD and Google in queue, Nvidia already targeting 1.6nm.

The battle for the most advanced process capacity at TSMC has officially begun. Global tech giants are accelerating their entry into the 2nm process node, with all capacity already booked. At the same time, advanced packaging supply is tightening, highlighting the persistent squeeze on the semiconductor supply chain from the overlapping demand for AI and mobile chips.

Nvidia CEO Jensen Huang, at a dinner with key supply chain executives on January 31, stated that TSMC must operate at full force this year, directly pointing out the tense situation with advanced process capacity. This statement confirms the industry's concerns over a shortage of TSMC's 2nm capacity.

According to industry sources, Apple has locked in more than half of the initial 2nm capacity, with Qualcomm also a major client for 2026. AMD plans to begin CPU production based on 2nm in 2026, while Google and AWS are targeting to introduce the process in Q3 and Q4 of 2027, respectively. Nvidia is looking further ahead to 2028, planning to use TSMC's A16 process for its Feynman AI GPU, which integrates back-side power delivery technology.

This capacity crunch is expected to last until 2027. AI accelerators and mobile processors are simultaneously competing for limited capacity, while the challenge of advanced packaging yields is further exacerbating supply-demand imbalances. Institutional investors expect TSMC's monthly CoWoS capacity to grow by more than 70% year-over-year in 2026, but it will still be difficult to meet market demand.

Mobile chips secure initial capacity, AI customers to scale up in 2027

Reports indicate that TSMC's 2nm and 3nm process nodes both face capacity constraints, with high-performance computing and mobile chips vying for limited supply. Apple's and Qualcomm's major 2nm orders are set for 2026. According to Wccftech citing sources, Apple has secured more than half of the initial 2nm output.

Starting in 2027, general GPUs and custom ASICs will begin to scale up production, including AMD’s MI series GPUs, Google’s eighth-generation TPU, and AWS’s Trainium 4. Industry insiders predict that TSMC’s 2nm family will become a long-lived node, with initial ramp-up possibly exceeding that of the 3nm generation.

The N2 process will enter mass production in 2026, with N2P and A16 processes following in the second half. Among them, the A16 process is targeted at specific high-performance computing products that require complex wiring and high-density power delivery.

Nvidia skips 2nm, heads straight to 1.6nm, betting on backside power delivery

Nvidia’s process roadmap reveals a different strategy. According to reports, the company plans to launch the Feynman AI GPU in 2028, expected to use TSMC’s A16 process, which features backside power delivery technology.

The A16 process represents TSMC’s 1.6nm node, designed specifically for high-performance computing. Backside power delivery technology moves the power delivery network to the back side of the chip, improving signal integrity and power efficiency, which is especially crucial for large AI accelerators.

This timeline means Nvidia may skip or only adopt 2nm on a limited scale, moving directly to the more advanced node—reflecting AI chipmakers' aggressive pursuit of leading-edge process technology.

Advanced packaging becomes new bottleneck, CoWoS capacity growth can’t keep up with demand

The bottleneck isn’t limited to wafer foundry. Reports indicate TSMC is upgrading its advanced packaging ecosystem. As AI chips move fully into chiplet architecture and ultra-large package sizes, single-chip designs can no longer meet computing demands, making CoWoS-L, SoIC, and hybrid bonding technologies effectively standard.

According to institutional investors cited in reports, TSMC aims for its monthly CoWoS capacity in 2026 to grow by over 70% year-over-year, and is gradually validating next-generation technologies such as CoWoP (Chip-on-Wafer-on-PCB) and CPO (Co-Packaged Optics).

Yet supply-demand imbalance remains a key bottleneck. Beyond the tight 2nm foundry capacity, improving yields for large-scale system-level packaging is another major challenge. As the package size of AI chips continues to expand, maintaining high yield becomes increasingly difficult, which could further limit supply capabilities for advanced chips.

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