TSMC's advanced packaging roadmap changes: CoWoS has a "longer lifecycle," and the next-generation CoPoS will arrive "at the earliest in Q4 2030."

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TSMC's advanced packaging technology roadmap is undergoing major adjustments. The mass production timeline for CoPoS has been significantly delayed, elevating the strategic importance of CoWoS. This change will profoundly impact the investment logic of the entire semiconductor packaging supply chain.

According to a DigiTimes report on Friday, due to greater-than-expected difficulties in advancing CoPoS, TSMC's latest plans indicate that the first batch of CoPoS packaging products will not be produced until the fourth quarter of 2030 at the earliest, which is roughly two years later than the previously expected 2028 mass production timeline.

At the same time, TSMC's CoWoS capacity for the next two years has already been fully booked, and the CoWoS lifecycle will be significantly extended compared to earlier expectations.

This adjustment means that supply chain vendors betting on early mass production of CoPoS now face the risk of missing their timelines, while equipment and material suppliers who continue to benefit from the expansion of CoWoS and SoIC can expect to maintain visibility on orders for a longer cycle. In addition, reports suggest that the CoWoP project led by Nvidia and SPIL may also be put on hold, further reshaping the market landscape.

Major Delay in CoPoS Timeline, with Technical Bottlenecks as the Main Reason

According to DigiTimes, citing supply chain sources, the core technical challenges faced by CoPoS are "uniformity" and "warpage". TSMC had already expected that the CoPoS mass production schedule would not move quickly.

From the latest planned timelines, TSMC will begin introducing equipment for R&D in the third quarter of 2026, with R&D line setup taking about a year. Equipment orders for the pilot line will be placed in the third quarter of 2027, with a lead time of about three quarters. The pilot equipment will enter the Chiayi P7 plant in the second quarter of 2028, after which about a year will still be needed for verification and adjustment. Mass production tools will be finalized and supply chain orders placed in mid to late 2029. After another three quarters for equipment delivery, equipment will be installed in the first quarter of 2030, and the first batch of packaging products could be produced as early as the fourth quarter of 2030.

Notably, TSMC is reported to have set extremely high requirements for suppliers participating in the joint development of CoPoS, even requiring some equipment vendors to sign restrictive contracts prohibiting the sale of related technologies or tools to other customers, further raising the participation threshold and development costs for the supply chain.

CoWoS and SoIC Expansion Accelerates, Nvidia Secures Key Capacities

Against the backdrop of CoPoS delays, the strategic value of CoWoS becomes increasingly prominent.

Not only Nvidia and AMD, but also ASIC customers are placing large orders, and TSMC's CoWoS capacity for the next two years has already been fully booked. The Tainan AP8 P1 plant is expected to have a monthly output of over 40,000 wafers by the end of this year, and the P2 facility is also under rapid construction.

For SoIC, TSMC plans to raise the Chiayi plant’s SoIC monthly capacity from the current nearly 10,000 wafers to 50,000 wafers by 2027. Nvidia will secure a large portion of this capacity, with about 10% to be used for co-packaged optics (CPO). This large-scale expansion is clearly positive for hybrid bonding equipment suppliers, and market analysts point out that related equipment orders are likely to follow.

Overall, with the continued expansion of CoWoS and accelerated volume production of SoIC, the supply risk for the supply chain in the next few years has decreased significantly compared to before, and the earnings visibility for equipment and material vendors has correspondingly increased.

CoWoP Project Faces Postponement, Supply Chain Landscape Reshaped

The CoWoP project jointly led by Nvidia and SPIL may be put on hold. The main reason is that this technical route is more challenging and costly, and participation interest from SPIL and Taiwanese PCB manufacturers is low.

The potential shelving of the CoWoP project further concentrates market attention on TSMC's own packaging technology roadmap. Against the dual backdrop of CoPoS mass production being a distant prospect and obstacles to the advancement of CoWoP, CoWoS and SoIC will remain the core pillars of TSMC's advanced packaging for a considerable time. As a result, the capital expenditure pace and order structure for the relevant supply chain will be repriced accordingly.

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